From fa9c9af4022ae80421c377867dabf6fb1dd1e22b Mon Sep 17 00:00:00 2001 From: Greg Still Date: Tue, 18 Oct 2016 13:05:21 -0500 Subject: p9_ppe_commands: add -step_trap support Change-Id: I734f2cafae2d6cb67b909459b80266052a988542 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31451 Tested-by: Jenkins Server Reviewed-by: ASHISH A. MORE Reviewed-by: Brian T. Vanderpool Reviewed-by: Gregory S. Still Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42287 Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell --- src/import/chips/p9/procedures/hwp/lib/p9_ppe_utils.H | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'src/import/chips/p9/procedures/hwp/lib/p9_ppe_utils.H') diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_ppe_utils.H b/src/import/chips/p9/procedures/hwp/lib/p9_ppe_utils.H index 03c3cfacf..656e2da9d 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_ppe_utils.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_ppe_utils.H @@ -64,12 +64,12 @@ typedef struct /** * @brief Offsets from base address for XIRs. */ -const static uint64_t PPE_XIXCR = 0x0; -const static uint64_t PPE_XIRAMRA = 0x1; -const static uint64_t PPE_XIRAMGA = 0x2; -const static uint64_t PPE_XIRAMDBG = 0x3; -const static uint64_t PPE_XIRAMEDR = 0x4; -const static uint64_t PPE_XIDBGPRO = 0x5; +const static uint64_t PPE_XIXCR = 0x0; //XCR_NONE +const static uint64_t PPE_XIRAMRA = 0x1; //XCR_SPRG0 +const static uint64_t PPE_XIRAMGA = 0x2; //IR_SPRG0 +const static uint64_t PPE_XIRAMDBG = 0x3; //XSR_SPRG0 +const static uint64_t PPE_XIRAMEDR = 0x4; //IR_EDR +const static uint64_t PPE_XIDBGPRO = 0x5; //XSR_IAR enum PPE_DUMP_MODE { -- cgit v1.2.1