From 923e7b0d61e159e645132b4e3f5fdf59c94d56bd Mon Sep 17 00:00:00 2001 From: Sumit Kumar Date: Tue, 24 Jul 2018 09:56:32 -0500 Subject: eRepair: Fixed records update for failed lanes in vpd - Fixed correct bit update for failed lane in vpd - Fixed max lane bandwidth of XBUS & DMI (upstream/downstream) - Corrected detection of dmi upstream/downstream that got swapped Change-Id: Ib48d4760027db4cdf1c8f44d85155f79d8a09b61 CQ:SW438579 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63210 Tested-by: Jenkins Server Tested-by: Hostboot CI Reviewed-by: Jennifer A. Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63229 Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Daniel M. Crowell --- src/import/chips/p9/procedures/hwp/io/p9_io_erepairConsts.H | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'src/import/chips/p9/procedures/hwp/io/p9_io_erepairConsts.H') diff --git a/src/import/chips/p9/procedures/hwp/io/p9_io_erepairConsts.H b/src/import/chips/p9/procedures/hwp/io/p9_io_erepairConsts.H index 134714929..8c16d1d2a 100755 --- a/src/import/chips/p9/procedures/hwp/io/p9_io_erepairConsts.H +++ b/src/import/chips/p9/procedures/hwp/io/p9_io_erepairConsts.H @@ -54,7 +54,7 @@ const uint8_t XBUS_2_ACTIVE_LANE_END = 15; const uint8_t XBUS_SPARE_DEPLOY_LANE_1 = 0; const uint8_t XBUS_MAXSPARES_IN_HW = 1; -const uint8_t XBUS_MAX_LANE_WIDTH = 16; +const uint8_t XBUS_MAX_LANE_WIDTH = 17; // O-Bus is 12+2 lanes wide. // Data lanes numbering: 0 - 11 @@ -65,9 +65,9 @@ const uint8_t OBUS_ACTIVE_LANE_END = 11; const uint8_t OBUS_SPARE_DEPLOY_LANE_1 = 0; const uint8_t OBUS_SPARE_DEPLOY_LANE_2 = 1; const uint8_t OBUS_MAXSPARES_IN_HW = 2; -const uint8_t OBUS_MAX_LANE_WIDTH = 12; +const uint8_t OBUS_MAX_LANE_WIDTH = 13; -// UpStream DMI-Bus is 21+2 lanes wide. +// UpStream DMI-Bus is 21+2+1(calibration) lanes wide. // Data lanes numbering: 0 - 20 // Spare lanes numbering: 21, 22 const uint8_t DMIBUS_UPSTREAM_ACTIVE_LANE_START = 0; @@ -82,8 +82,8 @@ const uint8_t DMIBUS_DOWNSTREAM_ACTIVE_LANE_END = 13; const uint8_t DMIBUS_SPARE_DEPLOY_LANE_1 = 0; const uint8_t DMIBUS_SPARE_DEPLOY_LANE_2 = 1; const uint8_t DMIBUS_MAXSPARES_IN_HW = 2; -const uint8_t DMIBUS_UPSTREAM_MAX_LANE_WIDTH = 21; -const uint8_t DMIBUS_DNSTREAM_MAX_LANE_WIDTH = 14; +const uint8_t DMIBUS_UPSTREAM_MAX_LANE_WIDTH = 24; +const uint8_t DMIBUS_DNSTREAM_MAX_LANE_WIDTH = 17; const uint32_t EREPAIR_P9_MODULE_VPD_FIELD_SIZE = 0x10E; // 270 bytes const uint32_t EREPAIR_P9_MODULE_VPD_MNFG_SIZE = 0x10E; // 270 bytes -- cgit v1.2.1