From 2619526afc04e9fe58c680ba67b93bd2d916283a Mon Sep 17 00:00:00 2001 From: Chris Steffen Date: Tue, 9 Jul 2019 15:28:40 -0400 Subject: P9A Tx Fifo Init + Init Settings Update - Added Tx Fifo Init Function to Dccal - Forced rx_dc_enable_cm_coarse_en = 0 - Updated P9A Filt Pll Attribute to select BG = 0 Change-Id: I7090856ba48886fb278e65814249a0166b7fe098 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/80218 Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Tested-by: HWSV CI Reviewed-by: Megan P. Nguyen Reviewed-by: Christian R. Geddes Reviewed-by: Jennifer A Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/80251 Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Christian R Geddes --- src/import/chips/p9/procedures/hwp/initfiles/p9a_omic_io_scom.C | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/import/chips/p9/procedures/hwp/initfiles') diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9a_omic_io_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9a_omic_io_scom.C index 3603135c4..6cf208fa3 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9a_omic_io_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9a_omic_io_scom.C @@ -250,6 +250,14 @@ fapi2::ReturnCode p9a_omic_io_scom(const fapi2::Target& (l_MCP_OMI0_IOO_CPLT_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_RC_ENABLE_AUTO_RECAL_OFF ); FAPI_TRY(fapi2::putScom(TGT0, 0x800970000701103full, l_scom_buffer)); } + { + FAPI_TRY(fapi2::getScom( TGT0, 0x800978000701103full, l_scom_buffer )); + + constexpr auto l_MCP_OMI0_IOO_CPLT_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DC_ENABLE_CM_COARSE_CAL_OFF = 0x0; + l_scom_buffer.insert<48, 1, 63, uint64_t> + (l_MCP_OMI0_IOO_CPLT_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DC_ENABLE_CM_COARSE_CAL_OFF ); + FAPI_TRY(fapi2::putScom(TGT0, 0x800978000701103full, l_scom_buffer)); + } { FAPI_TRY(fapi2::getScom( TGT0, 0x800988000701103full, l_scom_buffer )); -- cgit v1.2.1