From 074a2dd38f9a0ed7b944be505ffa2eb327abc341 Mon Sep 17 00:00:00 2001 From: Adam Hale Date: Mon, 3 Jun 2019 13:05:21 -0400 Subject: Axone int updates Change-Id: I6468addadd23f6f252ade88eacfd6a1fd2f47025 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/82625 Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Tested-by: HWSV CI Reviewed-by: Mark Pizzutillo Reviewed-by: Devon A Baughen Reviewed-by: Jennifer A Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/82636 Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Christian R Geddes --- .../chips/p9/initfiles/p9a.int.scan.initfile | 47 ++++++ .../chips/p9/initfiles/p9a.int.scom.initfile | 178 +++++++++++++++++++++ 2 files changed, 225 insertions(+) create mode 100644 src/import/chips/p9/initfiles/p9a.int.scan.initfile create mode 100644 src/import/chips/p9/initfiles/p9a.int.scom.initfile (limited to 'src/import/chips/p9/initfiles') diff --git a/src/import/chips/p9/initfiles/p9a.int.scan.initfile b/src/import/chips/p9/initfiles/p9a.int.scan.initfile new file mode 100644 index 000000000..745c936d3 --- /dev/null +++ b/src/import/chips/p9/initfiles/p9a.int.scan.initfile @@ -0,0 +1,47 @@ +#-- *!*************************************************************************** +#-- *! +#-- *! OWNER NAME : David Kauer (dmkauer@us.ibm.com) +#-- *! +#-- *!*************************************************************************** + + +SyntaxVersion = 3 + +target_type 0 TARGET_TYPE_PROC_CHIP; + +# Enabled for DD1 only +ispy INT.INT_PC_LBS1_CMD_MMIO_LDST_CS [when=L && ATTR_CHIP_EC_FEATURE_P9N_INT_DD10] { + bits, spyv; + 5, 0b1; + 6, 0b1; +} + +# Defect HW378025 / Nimbus DD1 only +ispy INT.INT_PC_LBS1_REGS_CLOCKGATE_DIS_CS [when=L && ATTR_CHIP_EC_FEATURE_HW378025] { + spyv; + 0b1; +} + +# Defect HW930007 / Nimbus DD1 only +ispy INT.INT_PC.LBS2.VPC.P1.LCBCNTL_BLK.CLOCKGATE_DISABLE [when=L && ATTR_CHIP_EC_FEATURE_HW930007] { + spyv; + 0b1; +} + +# Defect HW408972 / Nimbus DD1 & DD2 +ispy INT.INT_PC_LBS1_CRESP_MAC_CS [when=L && ATTR_CHIP_EC_FEATURE_HW408972] { + bits, spyv, expr; + 3, 0b1, ((ATTR_CHIP_EC_FEATURE_P9N_INT_DD10 == 1) || (ATTR_CHIP_EC_FEATURE_P9N_INT_DD20 == 1)); + 4, 0b1, (ATTR_CHIP_EC_FEATURE_P9N_INT_DD21 == 1); +} + +# Defect HW388874 +espy BRIDGE.PSIHB.ESB_OR_LSI_INTERRUPTS [when=L] { + spyv, expr; + ON, (ATTR_CHIP_EC_FEATURE_HW388874 == 0); +} +# HW441771 - Axone init to return to P9 behavior +ispy INT.INT_VC_LBS6_ARX_CS_AXONE_DISABLE_CILOAD_ORDERINGS [when=L && ATTR_CHIP_EC_FEATURE_AXONE_HW441771] { + spyv; + 0b1; +} diff --git a/src/import/chips/p9/initfiles/p9a.int.scom.initfile b/src/import/chips/p9/initfiles/p9a.int.scom.initfile new file mode 100644 index 000000000..5b0ff1886 --- /dev/null +++ b/src/import/chips/p9/initfiles/p9a.int.scom.initfile @@ -0,0 +1,178 @@ +#- *!*************************************************************************** +#-- *! +#-- *! OWNER NAME : David Kauer (dmkauer@us.ibm.com) +#-- *! +#-- *!*************************************************************************** + +SyntaxVersion = 3 + +target_type 0 TARGET_TYPE_PROC_CHIP; +target_type 1 TARGET_TYPE_SYSTEM; + +ispy INT.INT_PC.INT_PC_AIB_TX_CRD_RSD_CRD_VPC_LD_RMT [when=S && ATTR_CHIP_EC_FEATURE_P9N_INT_DD10] { + spyv; + 0b00; +} + +ispy INT.INT_VC.INT_VC_EQC_CONFIG_PAGE_OFFSET_CFG [when=S] { + spyv; + 0x5BBF; +} + +ispy INT.INT_VC.INT_VC_IRQ_TO_EQC_CREDITS [when=S] { + spyv; + 0x6262220242160000; +} + +# SW437676 / SW445631 +ispy INT.INT_VC.INT_VC_AIB_TIMEOUT [when=S] { + spyv; + 0x18; +} + +ispy INT.INT_PC.INT_PC_DBG_TMOT_ARX_TIMEOUT [when=S] { + spyv; + 0x18; +} + +ispy INT.INT_PC.INT_PC_DBG_TMOT_MMIO_LDST_TIMEOUT [when=S] { + spyv; + 0x18; +} + +# Defect HW372116 / Nimbus DD1 only +ispy INT.INT_CQ.INT_CQ_AIB_CTL [when=S && ATTR_CHIP_EC_FEATURE_HW372116] { + spyv; + 0x0070000072040140; +} + +# Defect HW395947 / Nimbus DD1 only +espy INT.INT_VC.INT_VC_AIB_TX_ORDERING_TAG_2_RELAXED_WR_ORDERING_DMA [when=S && ATTR_CHIP_EC_FEATURE_HW395947] { + spyv; + OFF; +} + +espy INT.INT_PC.INT_PC_AIB_TX_ORDER_RELAXED_WR_ORDERING [when=S && ATTR_CHIP_EC_FEATURE_HW395947] { + spyv; + OFF; +} + +# Error Configuration +ispy INT.INT_PC.INT_PC_ERR0_CFG0_ERROR_CONFIG0 [when=S] { + spyv, expr; + 0x010003FF00100020, (ATTR_CHIP_EC_FEATURE_HW426891 == 0); + 0x050043EF00100020, (ATTR_CHIP_EC_FEATURE_HW426891 == 1); +} + +ispy INT.INT_PC.INT_PC_ERR0_CFG1_ERROR_CONFIG0 [when=S] { + spyv, expr; + 0xD8DFB200DFAFFFD7, (ATTR_CHIP_EC_FEATURE_HW426891 == 0); + 0xFADFBB8CFFAFFFD7, (ATTR_CHIP_EC_FEATURE_HW426891 == 1); +} + +ispy INT.INT_PC.INT_PC_ERR1_CFG0_ERROR_CONFIG0 [when=S && ATTR_CHIP_EC_FEATURE_P9N_INT_DD10] { + spyv; + 0x0008002000002002; +} + +ispy INT.INT_PC.INT_PC_ERR1_CFG1_ERROR_CONFIG0 [when=S && ATTR_CHIP_EC_FEATURE_P9N_INT_DD10] { + spyv; + 0xEF6417D2DE7DD3FD; +} + +ispy INT.INT_PC.LBS2.INT_PC_VPC_ERR_CFG0_ERROR_CONFIG [when=S] { + spyv, expr; + 0x0002000410000000, (ATTR_CHIP_EC_FEATURE_HW426891 == 0); + 0x0002000610000000, (ATTR_CHIP_EC_FEATURE_HW426891 == 1); +} + +ispy INT.INT_PC.LBS2.INT_PC_VPC_ERR_CFG1_ERROR_CONFIG [when=S && ATTR_CHIP_EC_FEATURE_P9N_INT_DD10] { + spyv; + 0x7710CCC3E0000701; +} + +ispy INT.INT_VC.INT_VC_ERR_CFG_G0R0_ERROR_CONFIG [when=S && ATTR_CHIP_EC_FEATURE_P9N_INT_DD10] { + spyv; + 0x00001003000002; +} + +ispy INT.INT_VC.INT_VC_ERR_CFG_G0R1_ERROR_CONFIG [when=S && ATTR_CHIP_EC_FEATURE_P9N_INT_DD10] { + spyv; + 0xFFFFEFFCFFFFFC; +} + +ispy INT.INT_VC.INT_VC_ERR_CFG_G1R0_ERROR_CONFIG [when=S && ATTR_CHIP_EC_FEATURE_HW411637] { + spyv; + 0x0002C018006; +} + +ispy INT.INT_VC.INT_VC_ERR_CFG_G1R1_ERROR_CONFIG [when=S && ATTR_CHIP_EC_FEATURE_HW411637] { + spyv; + 0xFFFCFFEFFFA; +} + + +# FIR Registers +ispy INT.INT_CQ.INT_CQ_FIRMASK_FIR_MASK [when=S] { + spyv, expr; + 0x2000005C04028000, (ATTR_CHIP_EC_FEATURE_HW411637 == 1 && ATTR_CHIP_EC_FEATURE_HW426891 == 0); + 0x2000005C040281C3, (ATTR_CHIP_EC_FEATURE_HW411637 == 1 && ATTR_CHIP_EC_FEATURE_HW426891 == 1); + 0x0000005C040081C3, (ATTR_CHIP_EC_FEATURE_HW411637 == 0 && ATTR_CHIP_EC_FEATURE_HW426891 == 1); +} + +ispy INT.INT_CQ.INT_CQ_ACTION0_ACTION0 [when=S] { + spyv; + 0x0000000000000000; +} + +ispy INT.INT_CQ.INT_CQ_ACTION1_ACTION1 [when=S] { + spyv, expr; + 0x9554021F80110FCF, (ATTR_CHIP_EC_FEATURE_P9N_INT_DD10 == 1); + 0x9554021F80110E0C, (ATTR_CHIP_EC_FEATURE_P9N_INT_DD10 == 0); +} + + +# Dependent Dials +ispy INT.INT_CQ.INT_CQ_CFG_PB_GEN_ADDR_BAR_MODE [when=S] { + spyv; + 0; +} + +ispy INT.INT_CQ.INT_CQ_PBO_CTL_SKIP_G [when=S] { + spyv, expr; + 1 , (TGT1.ATTR_PROC_FABRIC_PUMP_MODE == ATTR_PROC_FABRIC_PUMP_MODE::CHIP_IS_GROUP); + 0 , (TGT1.ATTR_PROC_FABRIC_PUMP_MODE == ATTR_PROC_FABRIC_PUMP_MODE::CHIP_IS_NODE); +} + +ispy INT.INT_CQ.INT_CQ_CFG_PB_GEN_PUMP_MODE [when=S] { + spyv, expr; + 1 , (TGT1.ATTR_PROC_FABRIC_PUMP_MODE == ATTR_PROC_FABRIC_PUMP_MODE::CHIP_IS_GROUP); + 0 , (TGT1.ATTR_PROC_FABRIC_PUMP_MODE == ATTR_PROC_FABRIC_PUMP_MODE::CHIP_IS_NODE); +} + +ispy INT.INT_CQ.INT_CQ_CFG_PB_GEN_ADDR_EXT_MASK_EN_15_21 [when=S && ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE] { + bits, spyv; + 0:3, (TGT1.ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID); + 4:6, (TGT1.ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID); +} + +ispy INT.INT_CQ.INT_CQ_CFG_PB_GEN_SMF_CONFIG_0_1 [when=S && ATTR_CHIP_EC_FEATURE_SMF_SUPPORTED] { + spyv, expr; + 0b10, (TGT1.ATTR_SMF_CONFIG == TGT1.ATTR_SMF_CONFIG::ENABLED); +} + +# disable MCD for HW423589 +espy INT.INT_CQ.INT_CQ_PBO_CTL_DISABLE_G [when=S && ATTR_CHIP_EC_FEATURE_HW423589_OPTION1] { + spyv; + ON; +} + +espy INT.INT_CQ.INT_CQ_PBO_CTL_DISABLE_VG_NOT_SYS [when=S && ATTR_CHIP_EC_FEATURE_HW423589_OPTION1] { + spyv; + ON; +} +# HW441771 - Axone init to return to P9 behavior +ispy INT.INT_CQ.INT_CQ_PBI_CTL_RESERVED_25_31 [when=S && ATTR_CHIP_EC_FEATURE_AXONE_HW441771] { + spyv; + 0b1000000; +} -- cgit v1.2.1