From aed6647b5f801733dba1cd589f3360fa669d2584 Mon Sep 17 00:00:00 2001 From: Joachim Fenkes Date: Mon, 20 Nov 2017 17:22:21 +0100 Subject: p9*_clockcntl: Add missing NPU ring 0xF in N3 chiplet to clock check Correct nestn1 domain masks for partial good obuses Change-Id: I57efeff590a2b0a4830b19fbfff2eea09e16db2b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49909 Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Tested-by: HWSV CI Tested-by: Hostboot CI Reviewed-by: Benjamin Gass Dev-Ready: Benjamin Gass Reviewed-by: Joseph J. McGill Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50054 Reviewed-by: Hostboot Team Tested-by: Jenkins OP Build CI Reviewed-by: Daniel M. Crowell --- src/import/chips/p9/common/scominfo/p9_scom_addr.H | 1 + 1 file changed, 1 insertion(+) (limited to 'src/import/chips/p9/common') diff --git a/src/import/chips/p9/common/scominfo/p9_scom_addr.H b/src/import/chips/p9/common/scominfo/p9_scom_addr.H index ab424fb01..f866d8412 100644 --- a/src/import/chips/p9/common/scominfo/p9_scom_addr.H +++ b/src/import/chips/p9/common/scominfo/p9_scom_addr.H @@ -208,6 +208,7 @@ extern "C" N3_INT_0_RING_ID = 0xc, ///< INT_0 N3_PB_4_RING_ID = 0xd, ///< PB_4 N3_PB_5_RING_ID = 0xe, ///< PB_5 + N3_NPU_2_RING_ID = 0xf, ///< NPU_2 } p9_n3_ring_id_t; -- cgit v1.2.1