From c49249c720f42d201c92ef887930fee600fa34b5 Mon Sep 17 00:00:00 2001 From: Louis Stermole Date: Fri, 24 Jan 2020 10:55:11 -0500 Subject: Add Explorer specific MCBIST settings before scrub and maint Change-Id: Ieabf8b23b6670ed23664ce2f80b04012c05a4319 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/90287 Tested-by: FSP CI Jenkins Tested-by: HWSV CI Reviewed-by: STEPHEN GLANCY Tested-by: Jenkins Server Tested-by: Hostboot CI Dev-Ready: Louis Stermole Reviewed-by: ANDRE A MARIN Reviewed-by: Jennifer A Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/90317 Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Daniel M Crowell --- .../procedures/hwp/memory/exp_draminit_mc.C | 2 +- .../procedures/hwp/memory/lib/mc/exp_port.C | 57 ++++++++++++++++++++++ .../procedures/hwp/memory/lib/mc/exp_port.H | 17 ++++++- .../hwp/memory/lib/mcbist/exp_memdiags.C | 50 +++++++++++++++++++ 4 files changed, 124 insertions(+), 2 deletions(-) (limited to 'src/import/chips/ocmb/explorer/procedures/hwp') diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit_mc.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit_mc.C index bbc86d830..546299f57 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit_mc.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit_mc.C @@ -93,7 +93,7 @@ extern "C" FAPI_TRY( mss::enable_zq_cal(i_target), "%s Failed enable_zq_cal", mss::c_str(i_target) ); // Enable ecc checking - FAPI_TRY( mss::enable_read_ecc(i_target), "%s Failed enable_read_ecc", mss::c_str(i_target) ); + FAPI_TRY( mss::enable_read_ecc(i_target), "%s Failed enable_read_ecc", mss::c_str(i_target) ); // Apply marks from OCMB VPD FAPI_TRY( mss::apply_mark_store(i_target), "%s Failed enable_read_ecc", mss::c_str(i_target) ); diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/exp_port.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/exp_port.C index 31ad22e73..e4d733180 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/exp_port.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/exp_port.C @@ -22,3 +22,60 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file exp_port.C +/// @brief Code to support ports +/// +// *HWP HWP Owner: Stephen Glancy +// *HWP HWP Backup: Andre Marin +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: HB:FSP + +#include +#include +#include + +namespace mss +{ + +/// +/// @brief Set up memory controller specific settings for ECC registers (at the end of draminit_mc) +/// @param[in] i_target the target +/// @param[in,out] io_data contents of RECR register +/// @return FAPI2_RC_SUCCESS if and only if ok +/// @note mc_type::EXPLORER specialization +/// +template< > +fapi2::ReturnCode ecc_reg_settings_draminit_mc( + const fapi2::Target& i_target, + fapi2::buffer& io_data ) +{ + using TT = portTraits; + fapi2::buffer l_ctcr_data; + + // Explorer specific settings for RECR + io_data.setBit(); + io_data.setBit(); + io_data.clearBit(); + + // Set up CTCR timers to 20x4^3 (1280 clock cycles; typical read latency is 120ish, so this is about 10x) + // This is a preliminary guess from the design team. Also enable UE lockout window + // CTCR -> 51A8E00000000000 + FAPI_TRY( mss::getScom(i_target, TT::CTCR_REG, l_ctcr_data) ); + + l_ctcr_data.insertFromRight(0b010100); + l_ctcr_data.insertFromRight(0b011); + l_ctcr_data.insertFromRight(0b010100); + l_ctcr_data.insertFromRight(0b011); + l_ctcr_data.setBit(); + + FAPI_TRY( mss::putScom(i_target, TT::CTCR_REG, l_ctcr_data) ); + +fapi_try_exit: + return fapi2::current_err; +} + + +}// mss diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/exp_port.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/exp_port.H index 568dbbbbc..57646e97a 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/exp_port.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/exp_port.H @@ -76,6 +76,7 @@ class portTraits< mss::mc_type::EXPLORER > static constexpr uint64_t REFRESH_REG = EXPLR_SRQ_MBAREF0Q; static constexpr uint64_t STR0Q_REG = EXPLR_SRQ_MBASTR0Q; static constexpr uint64_t ECC_REG = EXPLR_RDF_RECR; + static constexpr uint64_t CTCR_REG = EXPLR_RDF_CTCR; static constexpr uint64_t DSM0Q_REG = EXPLR_SRQ_MBA_DSM0Q; static constexpr uint64_t FWMS_REG = EXPLR_RDF_FWMS0; @@ -111,10 +112,25 @@ class portTraits< mss::mc_type::EXPLORER > BW_SNAPSHOT = EXPLR_SRQ_MBA_FARB6Q_CFG_BW_SNAPSHOT, BW_SNAPSHOT_LEN = EXPLR_SRQ_MBA_FARB6Q_CFG_BW_SNAPSHOT_LEN, + RECR_ENABLE_MPE_NOISE_WINDOW = EXPLR_RDF_RECR_MBSECCQ_ENABLE_MPE_NOISE_WINDOW, RECR_ENABLE_UE_NOISE_WINDOW = EXPLR_RDF_RECR_MBSECCQ_ENABLE_UE_NOISE_WINDOW, RECR_TCE_CORRECTION = EXPLR_RDF_RECR_MBSECCQ_ENABLE_TCE_CORRECTION, RECR_MBSECCQ_DATA_INVERSION = EXPLR_RDF_RECR_MBSECCQ_DATA_INVERSION, RECR_MBSECCQ_DATA_INVERSION_LEN = EXPLR_RDF_RECR_MBSECCQ_DATA_INVERSION_LEN, + RECR_RETRY_UNMARKED_ERRORS = EXPLR_RDF_RECR_RETRY_UNMARKED_ERRORS, + RECR_CFG_MAINT_USE_TIMERS = EXPLR_RDF_RECR_CFG_MAINT_USE_TIMERS, + RECR_MBSECCQ_MAINT_NO_RETRY_UE = EXPLR_RDF_RECR_MBSECCQ_MAINT_NO_RETRY_UE, + RECR_MBSECCQ_MAINT_NO_RETRY_MPE = EXPLR_RDF_RECR_MBSECCQ_MAINT_NO_RETRY_MPE, + + CTCR_MPE_TIMER = EXPLR_RDF_CTCR_MPE_TIMER, + CTCR_MPE_TIMER_LEN = EXPLR_RDF_CTCR_MPE_TIMER_LEN, + CTCR_MPE_TIMEBASE = EXPLR_RDF_CTCR_MPE_TIMEBASE, + CTCR_MPE_TIMEBASE_LEN = EXPLR_RDF_CTCR_MPE_TIMEBASE_LEN, + CTCR_UE_TIMER = EXPLR_RDF_CTCR_UE_TIMER, + CTCR_UE_TIMER_LEN = EXPLR_RDF_CTCR_UE_TIMER_LEN, + CTCR_UE_TIMEBASE = EXPLR_RDF_CTCR_UE_TIMEBASE, + CTCR_UE_TIMEBASE_LEN = EXPLR_RDF_CTCR_UE_TIMEBASE_LEN, + CTCR_UE_LOCKOUT_ENABLE = EXPLR_RDF_CTCR_UE_LOCKOUT_ENABLE, DSM0Q_RDTAG_DLY = EXPLR_SRQ_MBA_DSM0Q_CFG_RDTAG_DLY, DSM0Q_RDTAG_DLY_LEN = EXPLR_SRQ_MBA_DSM0Q_CFG_RDTAG_DLY_LEN, @@ -187,7 +203,6 @@ fapi_try_exit: return fapi2::current_err; } - }// mss #endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_memdiags.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_memdiags.C index c4e2f807e..0c879abe9 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_memdiags.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_memdiags.C @@ -64,6 +64,56 @@ fapi2::ReturnCode operation::multi_port_init_internal() return single_port_init(); } +/// +/// @brief Set up memory controller specific settings for pre-maint mode read +/// @param[in] i_target the memory controller target +/// @return FAPI2_RC_SUCCESS iff ok +/// @note mc_type::EXPLORER specialization +/// +template<> +fapi2::ReturnCode pre_maint_read_settings( const fapi2::Target& + i_target ) +{ + using TT = mss::portTraits; + fapi2::buffer l_data; + + // Set up Explorer specific settings + FAPI_TRY( mss::getScom(i_target, TT::ECC_REG, l_data) ); + + l_data.setBit(); + l_data.setBit(); + + FAPI_TRY( mss::putScom(i_target, TT::ECC_REG, l_data) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Set up memory controller specific settings for pre-scrub +/// @param[in] i_target the memory controller target +/// @return FAPI2_RC_SUCCESS iff ok +/// @note mc_type::EXPLORER specialization +/// +template<> +fapi2::ReturnCode pre_scrub_settings( const fapi2::Target& + i_target ) +{ + using TT = mss::portTraits; + fapi2::buffer l_data; + + // Set up Explorer specific settings + FAPI_TRY( mss::getScom(i_target, TT::ECC_REG, l_data) ); + + l_data.clearBit(); + l_data.clearBit(); + + FAPI_TRY( mss::putScom(i_target, TT::ECC_REG, l_data) ); + +fapi_try_exit: + return fapi2::current_err; +} + } // namespace memdiags namespace exp -- cgit v1.2.1