From 12eac54482d5cbb72d53eda831646aa4ee9813f4 Mon Sep 17 00:00:00 2001 From: Louis Stermole Date: Wed, 22 Aug 2018 13:07:42 -0500 Subject: Re-enable training advanced WR_VREF algorithm in xml for p9c Change-Id: I7810246c4ff121ba619ce2635cfb916673522097 CQ:SW443239 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65017 Tested-by: Jenkins Server Reviewed-by: STEPHEN GLANCY Tested-by: HWSV CI Tested-by: Hostboot CI Reviewed-by: ANDRE A. MARIN Reviewed-by: Jennifer A. Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65030 Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Christian R. Geddes --- .../chips/centaur/procedures/xml/attribute_info/memory_attributes.xml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml') diff --git a/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml b/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml index ed52a9dac..915629447 100644 --- a/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml +++ b/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml @@ -114,11 +114,11 @@ Set by: PLL settings written by Dave Cadigan ATTR_CEN_MSS_VREF_CAL_CNTL TARGET_TYPE_MEMBUF_CHIP Training Control over IPL - ENUM - 0x00=DISABLE /Skip V-ref Train; 0x01=P8_DRAM - Enable V-Ref Train DRAM Level (P8 algorithm); 0x02=P8_RANK Level Training (P8 algorithm); 0x03=Box shmoo; 0x04=Ternary shmoo - Default Value = 0x00 for disabling training advanced on all platforms + Default Value = 0x04 for WR_VREF training on all platforms uint8 DISABLE = 0, P8_DRAM = 1, P8_RANK = 2, BOX = 3, TERNARY = 4 - DISABLE + TERNARY -- cgit v1.2.1