From fa0064292733ea0c5091de493ea52845ba8d9ecd Mon Sep 17 00:00:00 2001 From: Tsung Yeung Date: Mon, 8 Apr 2019 22:11:40 -0400 Subject: Ignore refresh overrun fir NVDIMM during post-restore sequence While CCS is running (ccs_addr_sel_mux=1) mainline refreshes could get queued up and later released 1 cycle apart, causing the refresh overrun fir. Mask this error during post-restore sequence so it doesn't get called out later. Change-Id: Iac0f998bfcc807d6f5fa2e6a57ec07a7afa5cc60 CQ:SW462190 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75692 Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Tested-by: HWSV CI Tested-by: Hostboot CI Reviewed-by: Louis Stermole Reviewed-by: STEPHEN GLANCY Reviewed-by: Thi N. Tran Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75696 Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Christian R. Geddes --- .../hwp/memory/lib/dimm/ddr4/nvdimm_utils.C | 14 ++++- .../hwp/memory/lib/dimm/ddr4/nvdimm_utils.H | 69 +++++++++++++++++++++- .../chips/p9/procedures/hwp/memory/lib/mc/port.H | 5 ++ .../hwp/memory/lib/workarounds/ccs_workarounds.C | 8 ++- 4 files changed, 89 insertions(+), 7 deletions(-) diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C index b35c5084f..869e18f25 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -70,7 +70,6 @@ namespace mss namespace nvdimm { - /// /// @brief Wrapper to read MAINT_ADDR_MODE_EN /// Specialization for TARGET_TYPE_MCA @@ -593,6 +592,7 @@ template<> fapi2::ReturnCode post_restore_transition( const fapi2::Target& i_target ) { mss::states l_maint_addr_enabled = mss::states::LOW; + mss::states l_refresh_overrun_mask = mss::states::OFF; const bool NVDIMM_WORKAROUND = true; FAPI_TRY(get_maint_addr_mode_en(i_target, l_maint_addr_enabled)); @@ -604,6 +604,10 @@ fapi2::ReturnCode post_restore_transition( const fapi2::Target #include #include +#include namespace mss { namespace nvdimm { +/// +/// @brief get refresh overrun fir mask +/// @param[in] i_target the target associated with this subroutine +/// @param[out] i_state the state to change to +/// @return FAPI2_RC_SUCCESS iff setup was successful +/// +inline fapi2::ReturnCode get_refresh_overrun_mask( const fapi2::Target& i_target, + mss::states& o_state ) +{ + typedef portTraits TT; + fapi2::buffer l_data; + + FAPI_TRY( mss::getScom(i_target, TT::CALFIRMASK, l_data), + "%s Failed getScom", mss::c_str(i_target) ); + + o_state = l_data.getBit() ? mss::states::ON : mss::states::OFF; + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief change refresh overrun fir mask +/// @param[in] i_target the target associated with this subroutine +/// @param[in] i_state the state to change to +/// @return FAPI2_RC_SUCCESS iff setup was successful +/// +inline fapi2::ReturnCode change_refresh_overrun_mask( const fapi2::Target& i_target, + const mss::states i_state ) +{ + typedef portTraits TT; + fapi2::buffer l_data; + + FAPI_TRY( mss::getScom(i_target, TT::CALFIRMASK, l_data), + "%s Failed getScom", mss::c_str(i_target) ); + + l_data.writeBit(i_state); + + FAPI_TRY( mss::putScom(i_target, TT::CALFIRMASK, l_data), + "%s Failed putScom", mss::c_str(i_target) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Clear the refresh overrun fir +/// @param[in] i_target the target associated with this subroutine +/// @return FAPI2_RC_SUCCESS iff setup was successful +/// +inline fapi2::ReturnCode clear_refresh_overrun_fir( const fapi2::Target& i_target ) +{ + typedef portTraits TT; + fapi2::buffer l_data; + + FAPI_TRY( mss::getScom(i_target, TT::CALFIRQ, l_data), + "%s Failed getScom", mss::c_str(i_target) ); + + l_data.clearBit(); + + FAPI_TRY( mss::putScom(i_target, TT::CALFIRQ, l_data), + "%s Failed putScom", mss::c_str(i_target) ); + +fapi_try_exit: + return fapi2::current_err; +} /// /// @brief Wrapper to read MAINT_ADDR_MODE_EN diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H index 252ebc5a9..45ffbee13 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H @@ -85,6 +85,8 @@ class portTraits static constexpr uint64_t CAL3Q_REG = MCA_MBA_CAL3Q; static constexpr uint64_t DSM0Q_REG = MCA_MBA_DSM0Q; static constexpr uint64_t FWMS_REG = MCA_FWMS0; + static constexpr uint64_t CALFIRQ = MCA_MBACALFIRQ; + static constexpr uint64_t CALFIRMASK = MCA_MBACALFIR_MASK; // Danger Will Robinson MCA_DDRPHY_PC_PER_ZCAL_CONFIG_P0 uses PHY rank ordinal numbers // which are different between PHYs. So if you're playing with this register, be sure to map rank numbers. @@ -238,6 +240,9 @@ class portTraits CAL3Q_ALL_PERIODIC_LENGTH_LEN = MCA_MBA_CAL3Q_CFG_ALL_PERIODIC_LENGTH_LEN, CAL3Q_FREEZE_ON_PARITY_ERROR_DIS = MCA_MBA_CAL3Q_CFG_FREEZE_ON_PARITY_ERROR_DIS, + CALFIRQ_REFRESH_OVERRUN = MCA_MBACALFIRQ_REFRESH_OVERRUN, + CALFIRMASK_REFRESH_OVERRUN = MCA_MBACALFIR_MASK_REFRESH_OVERRUN, + RECR_ENABLE_UE_NOISE_WINDOW = MCA_RECR_MBSECCQ_ENABLE_UE_NOISE_WINDOW, RECR_TCE_CORRECTION = MCA_RECR_MBSECCQ_ENABLE_TCE_CORRECTION, RECR_READ_POINTER_DLY = MCA_RECR_MBSECCQ_READ_POINTER_DELAY, diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/ccs_workarounds.C b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/ccs_workarounds.C index 13c3cffae..f6a8b3467 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/ccs_workarounds.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/ccs_workarounds.C @@ -241,6 +241,11 @@ fapi2::ReturnCode execute_inst_array(const fapi2::Target& stat_reg) -> bool { @@ -250,9 +255,6 @@ fapi2::ReturnCode execute_inst_array(const fapi2::Target