From df8f6df13fa6a7c4be88f5cf2d1070a4bee7711e Mon Sep 17 00:00:00 2001 From: Matt Derksen Date: Fri, 26 Apr 2019 09:33:19 -0500 Subject: Add gemini HWP calling into hostboot Added gem_getecid call in istep12. Adding NOOP calls for omi_setup, scominit, draminit_mc, and thermal_init if chip is Gemini. Change-Id: I677dd4dea0b39095c73d8b0769592ce68373ee6d RTC:204647 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76602 Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Glenn Miles Reviewed-by: Matthew Raybuck Reviewed-by: Daniel M. Crowell --- src/usr/isteps/istep12/call_dmi_io_run_training.C | 29 +- src/usr/isteps/istep12/call_mss_getecid.C | 182 +++++++++---- src/usr/isteps/istep12/makefile | 9 +- src/usr/isteps/istep13/call_mss_draminit_mc.C | 52 ++-- src/usr/isteps/istep13/call_mss_scominit.C | 308 +++++++++++++--------- src/usr/isteps/istep14/call_mss_thermal_init.C | 284 ++++++++++++++------ src/usr/isteps/istep14/makefile | 1 + 7 files changed, 582 insertions(+), 283 deletions(-) diff --git a/src/usr/isteps/istep12/call_dmi_io_run_training.C b/src/usr/isteps/istep12/call_dmi_io_run_training.C index 064a63a94..034683811 100644 --- a/src/usr/isteps/istep12/call_dmi_io_run_training.C +++ b/src/usr/isteps/istep12/call_dmi_io_run_training.C @@ -49,6 +49,7 @@ #ifdef CONFIG_AXONE #include #include +#include // for EXPLORER ID #endif using namespace ISTEP; @@ -114,15 +115,27 @@ void* call_dmi_io_run_training (void *io_pArgs) for (const auto & l_ocmb_target : l_ocmbTargetList) { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "exp_omi_setup HWP target HUID 0x%.08x", - TARGETING::get_huid(l_ocmb_target)); - // call the HWP with each target fapi2::Target l_fapi_ocmb_target - (l_ocmb_target); + (l_ocmb_target); - FAPI_INVOKE_HWP(l_err, exp_omi_setup, l_fapi_ocmb_target); + // check EXPLORER first as this is most likely the configuration + uint32_t chipId = l_ocmb_target->getAttr< TARGETING::ATTR_CHIP_ID>(); + if (chipId == POWER_CHIPID::EXPLORER_16) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "exp_omi_setup HWP target HUID 0x%.08x", + TARGETING::get_huid(l_ocmb_target)); + + FAPI_INVOKE_HWP(l_err, exp_omi_setup, l_fapi_ocmb_target); + } + else + { + // Gemini, just skip omi_setup call + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Skipping omi_setup HWP on target HUID 0x%.8X, chipId 0x%.4X", + TARGETING::get_huid(l_ocmb_target), chipId ); + } // process return code. if ( l_err ) @@ -143,8 +156,8 @@ void* call_dmi_io_run_training (void *io_pArgs) else { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS : exp_omi_setup HWP on target 0x%.08X, starting training", TARGETING::get_huid(l_ocmb_target)); - + "Start omi training on target HUID 0x%.8X", + TARGETING::get_huid(l_ocmb_target) ); FAPI_INVOKE_HWP(l_err, exp_omi_train, l_fapi_ocmb_target); // process return code. diff --git a/src/usr/isteps/istep12/call_mss_getecid.C b/src/usr/isteps/istep12/call_mss_getecid.C index 644661946..65b8bb1fc 100644 --- a/src/usr/isteps/istep12/call_mss_getecid.C +++ b/src/usr/isteps/istep12/call_mss_getecid.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -46,7 +46,14 @@ #include //HWP -#include +#ifndef CONFIG_AXONE + #include +#else + #include +// @todo RTC 208512 #include + #include +#endif + using namespace ISTEP; using namespace ISTEP_ERROR; @@ -56,10 +63,39 @@ using namespace TARGETING; namespace ISTEP_12 { +void cumulus_mss_getecid(IStepError & io_istepError); +void axone_mss_getecid(IStepError & io_istepError); + void* call_mss_getecid (void *io_pArgs) { IStepError l_StepError; + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_getecid entry" ); + auto l_procModel = TARGETING::targetService().getProcessorModel(); + + switch (l_procModel) + { + case TARGETING::MODEL_CUMULUS: + cumulus_mss_getecid(l_StepError); + break; + case TARGETING::MODEL_AXONE: + axone_mss_getecid(l_StepError); + break; + case TARGETING::MODEL_NIMBUS: + default: + break; + } + + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_getecid exit" ); + + // end task, returning any errorlogs to IStepDisp + return l_StepError.getErrorHandle(); +} + +#ifndef CONFIG_AXONE +void cumulus_mss_getecid(IStepError & io_istepError) +{ errlHndl_t l_err = NULL; uint8_t l_ddr_port_status = 0; uint8_t l_cache_enable = 0; @@ -71,28 +107,20 @@ void* call_mss_getecid (void *io_pArgs) { MSS_GET_CEN_ECID_DDR_STATUS_MBA0_BAD, MSS_GET_CEN_ECID_DDR_STATUS_MBA1_BAD }; - TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_getecid entry" ); - // Get all Centaur targets TARGETING::TargetHandleList l_membufTargetList; getAllChips(l_membufTargetList, TYPE_MEMBUF); - for (TargetHandleList::const_iterator - l_membuf_iter = l_membufTargetList.begin(); - l_membuf_iter != l_membufTargetList.end(); - ++l_membuf_iter) + for ( const auto & l_membuf_target : l_membufTargetList ) { - // make a local copy of the target for ease of use - TARGETING::Target* l_pCentaur = *l_membuf_iter; - // Dump current run on target TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "Running p9c_mss_get_cen_ecid HWP on " - "target HUID %.8X", TARGETING::get_huid(l_pCentaur)); + "target HUID %.8X", TARGETING::get_huid(l_membuf_target)); // call the HWP with each target fapi2::Target l_fapi_centaur - (l_pCentaur); + (l_membuf_target); // call the HWP with each fapi2::Target // Note: This HWP does not actually return the entire ECID data. It @@ -108,10 +136,10 @@ void* call_mss_getecid (void *io_pArgs) l_err->reasonCode()); // capture the target data in the elog - ErrlUserDetailsTarget(l_pCentaur).addToLog( l_err ); + ErrlUserDetailsTarget(l_membuf_target).addToLog( l_err ); // Create IStep error log and cross reference error that occurred - l_StepError.addErrorDetails( l_err ); + io_istepError.addErrorDetails( l_err ); // Commit Error errlCommit( l_err, HWPF_COMP_ID ); @@ -131,22 +159,14 @@ void* call_mss_getecid (void *io_pArgs) PredicateCTM l_mba_pred(CLASS_UNIT,TYPE_MBA); TARGETING::TargetHandleList l_mbaTargetList; getChildChiplets(l_mbaTargetList, - l_pCentaur, + l_membuf_target, TYPE_MBA); - uint8_t l_num_func_mbas = l_mbaTargetList.size(); - - for (TargetHandleList::const_iterator - l_mba_iter = l_mbaTargetList.begin(); - l_mba_iter != l_mbaTargetList.end(); - ++l_mba_iter) + for ( const auto & l_mba_target : l_mbaTargetList ) { - // Make a local copy of the target for ease of use - TARGETING::Target* l_pMBA = *l_mba_iter; - // Get the MBA chip unit position ATTR_CHIP_UNIT_type l_pos = - l_pMBA->getAttr(); + l_mba_target->getAttr(); // Check the DDR port status to see if this MBA should be // set to nonfunctional. @@ -154,10 +174,9 @@ void* call_mss_getecid (void *io_pArgs) { // call HWAS to deconfigure this target l_err = HWAS::theDeconfigGard().deconfigureTarget( - *l_pMBA, HWAS::DeconfigGard:: - DECONFIGURED_BY_MEMORY_CONFIG); - l_num_func_mbas--; - + *l_mba_target, + HWAS::DeconfigGard:: + DECONFIGURED_BY_MEMORY_CONFIG); if (l_err) { // shouldn't happen, but if it does, stop trying to @@ -173,7 +192,7 @@ void* call_mss_getecid (void *io_pArgs) "ERROR: error deconfiguring MBA or Centaur"); // Create IStep error log and cross ref error that occurred - l_StepError.addErrorDetails( l_err ); + io_istepError.addErrorDetails( l_err ); // Commit Error errlCommit( l_err, HWPF_COMP_ID ); @@ -212,12 +231,12 @@ void* call_mss_getecid (void *io_pArgs) // ATTR_CEN_MSS_CACHE_ENABLE is not set as writeable in src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml // Should we remove below code? // Set the ATTR_CEN_MSS_CACHE_ENABLE attribute - //l_pCentaur->setAttr( + //l_membuf_target->setAttr( // l_cache_enable); // Read the ATTR_CEN_MSS_CACHE_ENABLE back to pick up any override uint8_t l_cache_enable_attr = - l_pCentaur->getAttr(); + l_membuf_target->getAttr(); if (l_cache_enable != l_cache_enable_attr) { @@ -237,25 +256,21 @@ void* call_mss_getecid (void *io_pArgs) { // Deconfigure the L4 Cache Targets (there should be 1) TargetHandleList l_list; - getChildChiplets(l_list, l_pCentaur, TYPE_L4, false); + getChildChiplets(l_list, l_membuf_target, TYPE_L4, false); TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_getecid: deconfiguring %d L4s (Centaur huid: 0x%.8X)", - l_list.size(), get_huid(l_pCentaur)); + l_list.size(), get_huid(l_membuf_target)); - for (TargetHandleList::const_iterator - l_l4_iter = l_list.begin(); - l_l4_iter != l_list.end(); - ++l_l4_iter) + for ( const auto & l_l4_target : l_list ) { TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_getecid: deconfiguring L4 (huid: 0x%.8X)", - get_huid( *l_l4_iter)); + get_huid(l_l4_target)); l_err = HWAS::theDeconfigGard(). - deconfigureTarget(**l_l4_iter , - HWAS::DeconfigGard:: - DECONFIGURED_BY_MEMORY_CONFIG); + deconfigureTarget( *l_l4_target, + HWAS::DeconfigGard::DECONFIGURED_BY_MEMORY_CONFIG); if (l_err) { @@ -264,7 +279,7 @@ void* call_mss_getecid (void *io_pArgs) // Create IStep error log // and cross reference error that occurred - l_StepError.addErrorDetails( l_err); + io_istepError.addErrorDetails( l_err); // Commit Error errlCommit(l_err, HWPF_COMP_ID); @@ -281,11 +296,82 @@ void* call_mss_getecid (void *io_pArgs) TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "SUCCESS : mss_get_cen_ecid HWP( )" ); } +} +#else +void cumulus_mss_getecid(IStepError & io_istepError) +{ + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Error: Trying to call 'p9c_mss_get_cen_ecid' but Cumulus code is not compiled in"); + assert(0, "Calling wrong Model's HWPs"); +} +#endif - TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_getecid exit" ); +#ifdef CONFIG_AXONE +void axone_mss_getecid(IStepError & io_istepError) +{ + errlHndl_t l_err = NULL; - // end task, returning any errorlogs to IStepDisp - return l_StepError.getErrorHandle(); -} + // Get all OCMB targets + TARGETING::TargetHandleList l_ocmbTargetList; + getAllChips(l_ocmbTargetList, TYPE_OCMB_CHIP); + + bool isGeminiChip = false; + for (const auto & l_ocmb_target : l_ocmbTargetList) + { + fapi2::Target + l_fapi_ocmb_target(l_ocmb_target); + + // check EXPLORER first as this is most likely the configuration + uint32_t chipId = l_ocmb_target->getAttr< TARGETING::ATTR_CHIP_ID>(); + if (chipId == POWER_CHIPID::EXPLORER_16) + { + isGeminiChip = false; + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Running exp_getecid HWP on target HUID 0x%.8X", + TARGETING::get_huid(l_ocmb_target) ); + //@todo RTC 208512: FAPI_INVOKE_HWP(l_err, exp_getecid, l_fapi_ocmb_target); + } + else + { + isGeminiChip = true; + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Running gem_getecid HWP on target HUID 0x%.8X, chipId 0x%.4X", + TARGETING::get_huid(l_ocmb_target), chipId ); + FAPI_INVOKE_HWP(l_err, gem_getecid, l_fapi_ocmb_target); + } + + // process return code. + if ( l_err ) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR 0x%.8X : %s_getecid HWP returned error", + l_err->reasonCode(), isGeminiChip?"gem":"exp"); + + // capture the target data in the elog + ErrlUserDetailsTarget(l_ocmb_target).addToLog(l_err); + + // Create IStep error log and cross reference to error that occurred + io_istepError.addErrorDetails( l_err ); + // Commit Error + errlCommit( l_err, HWPF_COMP_ID ); + + break; + } + else + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS running %s_getecid HWP on target HUID 0x%.8X", + isGeminiChip?"gem":"exp", TARGETING::get_huid(l_ocmb_target) ); + } + } +} +#else +void axone_mss_getecid(IStepError & io_istepError) +{ + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Error: Trying to call 'gem_getecid' or 'exp_getecid' but Axone code is not compiled in"); + assert(0, "Calling wrong Model's HWPs"); +} +#endif }; diff --git a/src/usr/isteps/istep12/makefile b/src/usr/isteps/istep12/makefile index 45b7f463d..015ce6fa3 100644 --- a/src/usr/isteps/istep12/makefile +++ b/src/usr/isteps/istep12/makefile @@ -44,6 +44,9 @@ CENT_IO_HWP_PATH = $(CENT_PROC_PATH)/hwp/io CENT_MEM_HWP_PATH = $(CENT_PROC_PATH)/hwp/memory CENT_INITFILE_PATH = $(CENT_PROC_PATH)/hwp/initfiles +GEM_PROCEDURES_PATH = ${ROOTPATH}/src/import/chips/ocmb/gemini/procedures + + #Add all the extra include paths EXTRAINCDIR += ${ROOTPATH}/src/include/usr/fapi2/ EXTRAINCDIR += ${ROOTPATH}/src/import/hwpf/fapi2/include/ @@ -68,6 +71,9 @@ EXTRAINCDIR += ${P9A_MSS_HWP_PATH} EXTRAINCDIR += ${EXPLORER_HWP_PATH} EXTRAINCDIR += ${EXPLORER_INC_PATH} EXTRAINCDIR += ${P9A_MSS_ACCESSOR_PATH} +EXTRAINCDIR += ${GEM_PROCEDURES_PATH}/hwp/memory +EXTRAINCDIR += ${GEM_PROCEDURES_PATH}/hwp/memory/lib/ +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/common/utils VPATH += $(P9_NEST_HWP_PATH) VPATH += $(P9_PERV_HWP_PATH) @@ -125,6 +131,7 @@ VPATH += $(if $(CONFIG_AXONE),${P9A_MSS_HWP_PATH},) VPATH += $(if $(CONFIG_AXONE),${EXPLORER_HWP_PATH},) VPATH += $(if $(CONFIG_AXONE),${EXPLORER_OMI_HWP_PATH},) VPATH += $(if $(CONFIG_AXONE),${P9_MEMORY_HWP_PATH},) +VPATH += $(if $(CONFIG_AXONE),${GEM_PROCEDURES_PATH}/hwp/memory,) OBJS += $(if $(CONFIG_AXONE),exp_omi_utils.o,) OBJS += $(if $(CONFIG_AXONE),exp_omi_setup.o,) @@ -140,6 +147,6 @@ OBJS += $(if $(CONFIG_AXONE),p9a_omi_io_scom.o,) OBJS += $(if $(CONFIG_AXONE),p9a_omic_io_scom.o,) OBJS += $(if $(CONFIG_AXONE),p9a_io_omi_scominit.o,) OBJS += $(if $(CONFIG_AXONE),p9a_io_omi_dccal.o,) - +OBJS += $(if $(CONFIG_AXONE),gem_getecid.o,) include ${ROOTPATH}/config.mk diff --git a/src/usr/isteps/istep13/call_mss_draminit_mc.C b/src/usr/isteps/istep13/call_mss_draminit_mc.C index 0c7136298..54b790de2 100644 --- a/src/usr/isteps/istep13/call_mss_draminit_mc.C +++ b/src/usr/isteps/istep13/call_mss_draminit_mc.C @@ -46,6 +46,7 @@ #include #ifdef CONFIG_AXONE #include +#include // for EXPLORER ID #else #include #include @@ -124,8 +125,8 @@ void* call_mss_draminit_mc (void *io_pArgs) { // Dump current run on target TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "Running p9_mss_draminit_mc HWP on " - "target HUID %.8X", TARGETING::get_huid(l_membuf_target)); + "Running p9_mss_draminit_mc HWP on target HUID %.8X", + TARGETING::get_huid(l_membuf_target) ); fapi2::Target l_fapi_membuf_target (l_membuf_target); @@ -140,23 +141,24 @@ void* call_mss_draminit_mc (void *io_pArgs) l_err->reasonCode()); // capture the target data in the elog - ErrlUserDetailsTarget(l_fapi_membuf_target).addToLog( l_err ); + ErrlUserDetailsTarget(l_membuf_target).addToLog( l_err ); - // Create IStep error log and cross reference to error that occurred + // Create IStep error log and cross reference to error + // that occurred l_stepError.addErrorDetails( l_err ); // Commit Error errlCommit( l_err, HWPF_COMP_ID ); - + break; } else { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "SUCCESS running p9c_mss_draminit_mc HWP on " - "target HUID %.8X", TARGETING::get_huid(l_fapi_membuf_target)); + "target HUID %.8X", + TARGETING::get_huid(l_membuf_target)); } - } } @@ -168,17 +170,28 @@ void* call_mss_draminit_mc (void *io_pArgs) for (const auto & l_ocmb_target : l_ocmbTargetList) { - // Dump current run on target - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "Running exp_draminit_mc HWP on " - "target HUID %.8X", TARGETING::get_huid(l_ocmb_target)); - - fapi2::Target l_fapi_ocmb_target - (l_ocmb_target); + // check EXPLORER first as this is most likely the configuration + uint32_t chipId = l_ocmb_target->getAttr< TARGETING::ATTR_CHIP_ID>(); + if (chipId == POWER_CHIPID::EXPLORER_16) + { + fapi2::Target l_fapi_ocmb_target + (l_ocmb_target); - // call the HWP with each fapi2::Target - FAPI_INVOKE_HWP(l_err, exp_draminit_mc, l_fapi_ocmb_target); + // Dump current run on target + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Running exp_draminit_mc HWP on " + "target HUID %.8X", TARGETING::get_huid(l_ocmb_target)); + // call the HWP with each fapi2::Target + FAPI_INVOKE_HWP(l_err, exp_draminit_mc, l_fapi_ocmb_target); + } + else + { + // Gemini, NOOP + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Skipping draminit_mc HWP on target HUID 0x%.8X, chipId 0x%.4X", + TARGETING::get_huid(l_ocmb_target), chipId ); + } if (l_err) { TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, @@ -196,13 +209,12 @@ void* call_mss_draminit_mc (void *io_pArgs) break; } - else + else if (chipId == POWER_CHIPID::EXPLORER_16) { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS running exp_draminit_mc HWP on " - "target HUID %.8X", TARGETING::get_huid(l_ocmb_target)); + "SUCCESS running exp_draminit_mc HWP on target HUID %.8X", + TARGETING::get_huid(l_ocmb_target)); } - } #endif diff --git a/src/usr/isteps/istep13/call_mss_scominit.C b/src/usr/isteps/istep13/call_mss_scominit.C index 69e05c7ee..1b30268f0 100644 --- a/src/usr/isteps/istep13/call_mss_scominit.C +++ b/src/usr/isteps/istep13/call_mss_scominit.C @@ -46,6 +46,7 @@ #include #ifdef CONFIG_AXONE #include +#include // for EXPLORER ID #endif using namespace ERRORLOG; @@ -55,163 +56,220 @@ using namespace TARGETING; namespace ISTEP_13 { +void nimbus_call_mss_scominit(IStepError & io_istepError); +void cumulus_call_mss_scominit(IStepError & io_istepError); +void axone_call_mss_scominit(IStepError & io_istepError); + void* call_mss_scominit (void *io_pArgs) { - errlHndl_t l_err = NULL; - - IStepError l_stepError; + IStepError l_StepError; TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_scominit entry" ); + auto l_procModel = TARGETING::targetService().getProcessorModel(); + + switch (l_procModel) + { + case TARGETING::MODEL_CUMULUS: + cumulus_call_mss_scominit(l_StepError); + break; + case TARGETING::MODEL_AXONE: + axone_call_mss_scominit(l_StepError); + break; + case TARGETING::MODEL_NIMBUS: + nimbus_call_mss_scominit(l_StepError); + break; + default: + assert(0, "call_mss_scominit: Unsupported model type 0x%04X", + l_procModel); + break; + } + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_scominit exit" ); - do + // end task, returning any errorlogs to IStepDisp + return l_StepError.getErrorHandle(); +} + +#ifndef CONFIG_AXONE + +void nimbus_call_mss_scominit(IStepError & io_istepError) +{ + errlHndl_t l_err = nullptr; + + // Get all MCBIST targets + TARGETING::TargetHandleList l_mcbistTargetList; + getAllChiplets(l_mcbistTargetList, TYPE_MCBIST); + + for (const auto & l_target : l_mcbistTargetList) { - // Get all MCBIST targets - TARGETING::TargetHandleList l_mcbistTargetList; - getAllChiplets(l_mcbistTargetList, TYPE_MCBIST); + // Dump current run on target + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Running p9_mss_scominit HWP on target HUID %.8X", + TARGETING::get_huid(l_target)); + + fapi2::Target l_fapi_target + (l_target); + + // call the HWP with each fapi2::Target + FAPI_INVOKE_HWP(l_err, p9_mss_scominit, l_fapi_target); - for (const auto & l_target : l_mcbistTargetList) + if (l_err) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR 0x%.8X: p9_mss_scominit HWP returns error", + l_err->reasonCode()); + + // capture the target data in the elog + ErrlUserDetailsTarget(l_target).addToLog(l_err); + + // Create IStep error log and cross reference to error that + // occurred + io_istepError.addErrorDetails( l_err ); + + // Commit Error + errlCommit( l_err, HWPF_COMP_ID ); + + break; + } + else { - // Dump current run on target TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "Running p9_mss_scominit HWP on " - "target HUID %.8X", + "SUCCESS running p9_mss_scominit HWP on target HUID %.8X", TARGETING::get_huid(l_target)); + } + } +} - fapi2::Target l_fapi_target - (l_target); +void cumulus_call_mss_scominit(IStepError & io_istepError) +{ + errlHndl_t l_err = nullptr; - // call the HWP with each fapi2::Target - FAPI_INVOKE_HWP(l_err, p9_mss_scominit, l_fapi_target); - - if (l_err) - { - TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR 0x%.8X: p9_mss_scominit HWP returns error", - l_err->reasonCode()); - - // capture the target data in the elog - ErrlUserDetailsTarget(l_target).addToLog(l_err); - - // Create IStep error log and cross reference to error that - // occurred - l_stepError.addErrorDetails( l_err ); - - // Commit Error - errlCommit( l_err, HWPF_COMP_ID ); - - break; - } - else - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS running p9_mss_scominit HWP on " - "target HUID %.8X", TARGETING::get_huid(l_target)); - } - } + // Get all MBA targets + TARGETING::TargetHandleList l_membufTargetList; + getAllChips(l_membufTargetList, TYPE_MEMBUF); + + for (const auto & l_membuf_target : l_membufTargetList) + { + // Dump current run on target + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Running p9c_mss_scominit HWP on target HUID %.8X", + TARGETING::get_huid(l_membuf_target)); + + fapi2::Target l_fapi_membuf_target + (l_membuf_target); + + // call the HWP with each fapi2::Target + FAPI_INVOKE_HWP(l_err, p9c_mss_scominit, l_fapi_membuf_target); - if (!l_stepError.isNull()) + if (l_err) { - break; - } + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR 0x%.8X: p9c_mss_scominit HWP returns error", + l_err->reasonCode()); + + // capture the target data in the elog + ErrlUserDetailsTarget(l_membuf_target).addToLog(l_err); - // Get all MBA targets - TARGETING::TargetHandleList l_membufTargetList; - getAllChips(l_membufTargetList, TYPE_MEMBUF); + // Create IStep error log and cross reference to error that + // occurred + io_istepError.addErrorDetails( l_err ); - for (const auto & l_membuf_target : l_membufTargetList) + // Commit Error + errlCommit( l_err, HWPF_COMP_ID ); + + break; + } + else { - // Dump current run on target TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "Running p9c_mss_scominit HWP on " - "target HUID %.8X", - TARGETING::get_huid(l_membuf_target)); + "SUCCESS running p9c_mss_scominit HWP on target HUID %.8X", + TARGETING::get_huid(l_membuf_target)); + } + } +} +#else +void nimbus_call_mss_scominit(IStepError & io_istepError) +{ + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Error: Trying to call 'p9_mss_scominit' but Nimbus code is not compiled in"); + assert(0, "Calling wrong Model's HWPs"); +} - fapi2::Target l_fapi_membuf_target - (l_membuf_target); +void cumulus_call_mss_scominit(IStepError & io_istepError) +{ + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Error: Trying to call 'p9c_mss_scominit' but Cumulus code is not compiled in"); + assert(0, "Calling wrong Model's HWPs"); +} + +#endif - // call the HWP with each fapi2::Target - FAPI_INVOKE_HWP(l_err, p9c_mss_scominit, l_fapi_membuf_target); - - if (l_err) - { - TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR 0x%.8X: p9c_mss_scominit HWP returns error", - l_err->reasonCode()); - - // capture the target data in the elog - ErrlUserDetailsTarget(l_membuf_target).addToLog(l_err); - - // Create IStep error log and cross reference to error that - // occurred - l_stepError.addErrorDetails( l_err ); - - // Commit Error - errlCommit( l_err, HWPF_COMP_ID ); - - break; - } - else - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS running p9c_mss_scominit HWP on " - "target HUID %.8X", TARGETING::get_huid(l_membuf_target)); - } - } #ifdef CONFIG_AXONE - // Get all OCMB targets - TARGETING::TargetHandleList l_ocmbTargetList; - getAllChips(l_ocmbTargetList, TYPE_OCMB_CHIP); +void axone_call_mss_scominit(IStepError & io_istepError) +{ + errlHndl_t l_err = nullptr; - for (const auto & l_ocmb_target : l_ocmbTargetList) - { - // Dump current run on target - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "Running exp_scominit HWP on " - "target HUID %.8X", - TARGETING::get_huid(l_ocmb_target)); + // Get all OCMB targets + TARGETING::TargetHandleList l_ocmbTargetList; + getAllChips(l_ocmbTargetList, TYPE_OCMB_CHIP); + for (const auto & l_ocmb_target : l_ocmbTargetList) + { + // check EXPLORER first as this is most likely the configuration + uint32_t chipId = l_ocmb_target->getAttr< TARGETING::ATTR_CHIP_ID>(); + if (chipId == POWER_CHIPID::EXPLORER_16) + { fapi2::Target l_fapi_ocmb_target (l_ocmb_target); + // Dump current run on target + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Running exp_scominit HWP on target HUID %.8X", + TARGETING::get_huid(l_ocmb_target)); + // call the HWP with each fapi2::Target FAPI_INVOKE_HWP(l_err, exp_scominit, l_fapi_ocmb_target); - - if (l_err) - { - TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR 0x%.8X: exp_scominit HWP returns error", - l_err->reasonCode()); - - // capture the target data in the elog - ErrlUserDetailsTarget(l_fapi_ocmb_target).addToLog(l_err); - - // Create IStep error log and cross reference to error that - // occurred - l_stepError.addErrorDetails( l_err ); - - // Commit Error - errlCommit( l_err, HWPF_COMP_ID ); - - break; - } - else - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS running exp_scominit HWP on " - "target HUID %.8X", TARGETING::get_huid(l_ocmb_target)); - } } - - if (!l_stepError.isNull()) + else { - break; + // Gemini, NOOP + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Skipping scominit HWP on target HUID 0x%.8X, chipId 0x%.4X", + TARGETING::get_huid(l_ocmb_target), chipId ); } -#endif - } while (0); + if (l_err) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR 0x%.8X: exp_scominit HWP returns error", + l_err->reasonCode()); - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_scominit exit" ); - return l_stepError.getErrorHandle(); -} + // capture the target data in the elog + ErrlUserDetailsTarget(l_ocmb_target).addToLog(l_err); + + // Create IStep error log and cross reference to error that + // occurred + io_istepError.addErrorDetails( l_err ); + // Commit Error + errlCommit( l_err, HWPF_COMP_ID ); + + break; + } + else if (chipId == POWER_CHIPID::EXPLORER_16) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS running exp_scominit HWP on " + "target HUID %.8X", TARGETING::get_huid(l_ocmb_target)); + } + } +} +#else +void axone_call_mss_scominit(IStepError & io_istepError) +{ + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Error: Trying to call 'exp_scominit' but Axone code is not compiled in"); + assert(0, "Calling wrong Model's HWPs"); +} +#endif }; diff --git a/src/usr/isteps/istep14/call_mss_thermal_init.C b/src/usr/isteps/istep14/call_mss_thermal_init.C index 8e00df762..046260673 100644 --- a/src/usr/isteps/istep14/call_mss_thermal_init.C +++ b/src/usr/isteps/istep14/call_mss_thermal_init.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -41,6 +41,10 @@ #include #include +#ifdef CONFIG_AXONE + //@TODO RTC:195557 #include + #include // for EXPLORER ID +#endif using namespace ISTEP; using namespace ISTEP_ERROR; @@ -49,43 +53,78 @@ using namespace TARGETING; namespace ISTEP_14 { +void nimbus_call_mss_thermal_init(IStepError & io_istepError); +void cumulus_call_mss_thermal_init(IStepError & io_istepError); +void axone_call_mss_thermal_init(IStepError & io_istepError); +void run_proc_throttle_sync(IStepError & io_istepError); + void* call_mss_thermal_init (void *io_pArgs) { IStepError l_StepError; + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_thermal_init entry"); + + auto l_procModel = TARGETING::targetService().getProcessorModel(); + switch (l_procModel) + { + case TARGETING::MODEL_CUMULUS: + cumulus_call_mss_thermal_init(l_StepError); + break; + case TARGETING::MODEL_AXONE: + axone_call_mss_thermal_init(l_StepError); + break; + case TARGETING::MODEL_NIMBUS: + nimbus_call_mss_thermal_init(l_StepError); + break; + default: + assert(0, "call_mss_thermal_init: Unsupported model type 0x%04X", + l_procModel); + break; + } + + run_proc_throttle_sync(l_StepError); + + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_thermal_init exit"); + + // end task, returning any errorlogs to IStepDisp + return l_StepError.getErrorHandle(); +} + +#ifndef CONFIG_AXONE +void nimbus_call_mss_thermal_init(IStepError & io_istepError) +{ errlHndl_t l_errl = nullptr; - // -- Cumulus only --- - // Get all Centaur targets - TARGETING::TargetHandleList l_memBufTargetList; - getAllChips(l_memBufTargetList, TYPE_MEMBUF); + // -- Nimbus only --- + // Get all MCS targets + TARGETING::TargetHandleList l_mcsTargetList; + getAllChiplets(l_mcsTargetList, TYPE_MCS); // -------------------------------------------------------------------- - // run mss_thermal_init on all functional Centaur chips + // run mss_thermal_init on all functional MCS chiplets // -------------------------------------------------------------------- - for (auto l_pCentaur : l_memBufTargetList) + for (const auto & l_pMcs : l_mcsTargetList) { - fapi2::Target l_fapi_pCentaur - (l_pCentaur); + fapi2::Target l_fapi_pMcs(l_pMcs); // Current run on target TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "Running call_mss_thermal_init HWP on " - "target HUID %.8X", TARGETING::get_huid(l_pCentaur)); + "Running p9_mss_thermal_init HWP on target HUID %.8X", + TARGETING::get_huid(l_pMcs) ); - FAPI_INVOKE_HWP( l_errl, p9c_mss_thermal_init, l_fapi_pCentaur ); + FAPI_INVOKE_HWP( l_errl, p9_mss_thermal_init, l_fapi_pMcs ); if ( l_errl ) { TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR 0x%.8X: p9c_mss_thermal_init HWP returns error", + "ERROR 0x%.8X: p9_mss_thermal_init HWP returns error", l_errl->reasonCode()); // capture the target data in the elog - ErrlUserDetailsTarget(l_pCentaur).addToLog( l_errl ); + ErrlUserDetailsTarget(l_pMcs).addToLog( l_errl ); // Create IStep error log and cross reference // to error that occurred - l_StepError.addErrorDetails( l_errl ); + io_istepError.addErrorDetails( l_errl ); // Commit Error errlCommit( l_errl, HWPF_COMP_ID ); @@ -94,43 +133,50 @@ void* call_mss_thermal_init (void *io_pArgs) } else { - TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS : p9c_mss_thermal_init HWP( )" ); + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS : p9_mss_thermal_init HWP() on 0x%.8X MCS", + TARGETING::get_huid(l_pMcs) ); } - } + } // end MCS loop - // -- Nimbus only --- - // Get all MCS targets - TARGETING::TargetHandleList l_mcsTargetList; - getAllChiplets(l_mcsTargetList, TYPE_MCS); +} + +void cumulus_call_mss_thermal_init(IStepError & io_istepError) +{ + errlHndl_t l_errl = nullptr; + + // -- Cumulus only --- + // Get all Centaur targets + TARGETING::TargetHandleList l_memBufTargetList; + getAllChips(l_memBufTargetList, TYPE_MEMBUF); // -------------------------------------------------------------------- - // run mss_thermal_init on all functional MCS chiplets + // run mss_thermal_init on all functional Centaur chips // -------------------------------------------------------------------- - for (auto l_pMcs : l_mcsTargetList) + for (const auto & l_pCentaur : l_memBufTargetList) { - fapi2::Target l_fapi_pMcs - (l_pMcs); + fapi2::Target l_fapi_pCentaur + (l_pCentaur); // Current run on target TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "Running call_mss_thermal_init HWP on " - "target HUID %.8X", TARGETING::get_huid(l_pMcs)); + "Running p9c_mss_thermal_init HWP on target HUID %.8X", + TARGETING::get_huid(l_pCentaur) ); - FAPI_INVOKE_HWP( l_errl, p9_mss_thermal_init, l_fapi_pMcs ); + FAPI_INVOKE_HWP( l_errl, p9c_mss_thermal_init, l_fapi_pCentaur ); if ( l_errl ) { TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR 0x%.8X: p9_mss_thermal_init HWP returns error", + "ERROR 0x%.8X: p9c_mss_thermal_init HWP returns error", l_errl->reasonCode()); // capture the target data in the elog - ErrlUserDetailsTarget(l_pMcs).addToLog( l_errl ); + ErrlUserDetailsTarget(l_pCentaur).addToLog( l_errl ); // Create IStep error log and cross reference // to error that occurred - l_StepError.addErrorDetails( l_errl ); + io_istepError.addErrorDetails( l_errl ); // Commit Error errlCommit( l_errl, HWPF_COMP_ID ); @@ -139,70 +185,146 @@ void* call_mss_thermal_init (void *io_pArgs) } else { - TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS : p9_mss_thermal_init HWP( )" ); + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS : p9c_mss_thermal_init HWP( ) on 0x%.8X target", + TARGETING::get_huid(l_pCentaur) ); } - } + } // end MEMBUF loop +} +#else +void nimbus_call_mss_thermal_init(IStepError & io_istepError) +{ + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Error: Trying to call 'p9_mss_thermal_init' but Nimbus code is not compiled in"); + assert(0, "Calling wrong Model's HWPs"); +} - do +void cumulus_call_mss_thermal_init(IStepError & io_istepError) +{ + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Error: Trying to call 'p9c_mss_thermal_init' but Cumulus code is not compiled in"); + assert(0, "Calling wrong Model's HWPs"); +} +#endif + +#ifdef CONFIG_AXONE +void axone_call_mss_thermal_init(IStepError & io_istepError) +{ + errlHndl_t l_err = nullptr; + + // Get all OCMB targets + TARGETING::TargetHandleList l_ocmbTargetList; + getAllChips(l_ocmbTargetList, TYPE_OCMB_CHIP); + + for (const auto & l_ocmb_target : l_ocmbTargetList) { - // Run proc throttle sync - // Get all functional proc chip targets - //Use targeting code to get a list of all processors - TARGETING::TargetHandleList l_procChips; - getAllChips( l_procChips, TARGETING::TYPE_PROC ); + // check EXPLORER first as this is most likely the configuration + uint32_t chipId = l_ocmb_target->getAttr< TARGETING::ATTR_CHIP_ID>(); + if (chipId == POWER_CHIPID::EXPLORER_16) + { + fapi2::Target l_fapi_ocmb_target + (l_ocmb_target); - for (const auto & l_procChip: l_procChips) + // Dump current run on target + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Running exp_thermal_init HWP on target HUID %.8X", + TARGETING::get_huid(l_ocmb_target)); + + // call the HWP with each fapi2::Target + // @todo RTC 195557 FAPI_INVOKE_HWP(l_err, exp_thermal_init, l_fapi_ocmb_target); + } + else + { + // Gemini, NOOP + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Skipping thermal_init HWP on axone target HUID 0x%.8X, chipId 0x%.4X", + TARGETING::get_huid(l_ocmb_target), chipId ); + } + + if (l_err) { - //Convert the TARGETING::Target into a fapi2::Target by passing - //l_procChip into the fapi2::Target constructor - fapi2::Target - l_fapi2CpuTarget((l_procChip)); + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR 0x%.8X: exp_thermalinit HWP returns error", + l_err->reasonCode()); + + // capture the target data in the elog + ErrlUserDetailsTarget(l_ocmb_target).addToLog(l_err); + + // Create IStep error log and cross reference to error that + // occurred + io_istepError.addErrorDetails( l_err ); + // Commit Error + errlCommit( l_err, HWPF_COMP_ID ); + + break; + } + else if (chipId == POWER_CHIPID::EXPLORER_16) + { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "Running p9_throttle_sync HWP on " - "target HUID %.8X", TARGETING::get_huid(l_procChip)); - - // Call p9_throttle_sync - FAPI_INVOKE_HWP( l_errl, p9_throttle_sync, l_fapi2CpuTarget ); - - if (l_errl) - { - TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR 0x%.8X: p9_throttle_sync HWP returns error", - l_errl->reasonCode()); - - // Capture the target data in the elog - ErrlUserDetailsTarget(l_procChip).addToLog(l_errl); - - // Create IStep error log and cross reference - // to error that occurred - l_StepError.addErrorDetails( l_errl ); - - // Commit Error - errlCommit( l_errl, HWPF_COMP_ID ); - - break; - } - else - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS : p9_throttle_sync HWP( )" ); - } + "SUCCESS running exp_thermalinit HWP on target HUID %.8X", + TARGETING::get_huid(l_ocmb_target)); } + } // end OCMB loop +} +#else +void axone_call_mss_thermal_init(IStepError & io_istepError) +{ + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Error: Trying to call 'exp_thermal_init' but Axone code is not compiled in"); + assert(0, "Calling wrong Model's HWPs"); +} +#endif - } while (0); +void run_proc_throttle_sync(IStepError & io_istepError) +{ + errlHndl_t l_errl = nullptr; + // Run proc throttle sync + // Get all functional proc chip targets + // Use targeting code to get a list of all processors + TARGETING::TargetHandleList l_procChips; + getAllChips( l_procChips, TARGETING::TYPE_PROC ); - if(l_StepError.isNull()) + for (const auto & l_procChip: l_procChips) { + //Convert the TARGETING::Target into a fapi2::Target by passing + //l_procChip into the fapi2::Target constructor + fapi2::Target + l_fapi2CpuTarget((l_procChip)); + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS : call_mss_thermal_init" ); - } + "Running p9_throttle_sync HWP on target HUID %.8X", + TARGETING::get_huid(l_procChip) ); + // Call p9_throttle_sync + FAPI_INVOKE_HWP( l_errl, p9_throttle_sync, l_fapi2CpuTarget ); - // end task, returning any errorlogs to IStepDisp - return l_StepError.getErrorHandle(); + if (l_errl) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR 0x%.8X: p9_throttle_sync HWP returns error", + l_errl->reasonCode()); + + // Capture the target data in the elog + ErrlUserDetailsTarget(l_procChip).addToLog(l_errl); + + // Create IStep error log and cross reference + // to error that occurred + io_istepError.addErrorDetails( l_errl ); + + // Commit Error + errlCommit( l_errl, HWPF_COMP_ID ); + + break; + } + else + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS : p9_throttle_sync HWP( ) on 0x%.8X processor", + TARGETING::get_huid(l_procChip) ); + } + } } }; diff --git a/src/usr/isteps/istep14/makefile b/src/usr/isteps/istep14/makefile index 47c6c15e6..788232ccd 100644 --- a/src/usr/isteps/istep14/makefile +++ b/src/usr/isteps/istep14/makefile @@ -50,6 +50,7 @@ EXTRAINCDIR += ${ROOTPATH}/src/import/chips/centaur/common/include/ EXTRAINCDIR += ${PROCEDURE_PATH}/hwp/memory/lib/dimm/ddr4/ EXTRAINCDIR += ${EXP_COMMON_PATH}/include/ EXTRAINCDIR += ${ROOTPATH}/src/import/chips/ocmb/explorer/procedures/hwp/memory +EXTRAINCDIR += ${ROOTPATH}/src/import/chips/common/utils OBJS += call_mss_memdiag.o OBJS += call_mss_thermal_init.o -- cgit v1.2.1