From df4522fe41d2857238861d8dec260fd4fa6aba38 Mon Sep 17 00:00:00 2001 From: Prachi Gupta Date: Tue, 10 Mar 2015 11:49:45 -0500 Subject: SW292676: INITPROC: FSP&Hostboot - Catch up file versions - no function Change-Id: I5b18c640be03572ccf802a91f46b2acd15238d3f CQ:SW292676 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/15465 Reviewed-by: PRACHI GUPTA Reviewed-by: Sangeetha T S Tested-by: Sangeetha T S Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/16273 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III --- src/usr/hwpf/hwp/bus_training/io_clear_firs.H | 5 +++-- .../hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C | 12 ++++++++---- src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile | 5 ++++- .../mss_eff_config/memory_mss_bulk_pwr_throttles.xml | 6 ++++-- 4 files changed, 19 insertions(+), 9 deletions(-) diff --git a/src/usr/hwpf/hwp/bus_training/io_clear_firs.H b/src/usr/hwpf/hwp/bus_training/io_clear_firs.H index 01ac598a1..1c8811e3e 100644 --- a/src/usr/hwpf/hwp/bus_training/io_clear_firs.H +++ b/src/usr/hwpf/hwp/bus_training/io_clear_firs.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2014 */ +/* Contributors Listed Below - COPYRIGHT 2013,2015 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -22,7 +22,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: io_clear_firs.H,v 1.8 2013/08/01 12:57:19 varkeykv Exp $ +// $Id: io_clear_firs.H,v 1.11 2014/07/22 12:35:23 jaswamin Exp $ // *!*************************************************************************** // *! (C) Copyright International Business Machines Corp. 2012, 2013 // *! All Rights Reserved -- Property of IBM @@ -41,6 +41,7 @@ //------------------------------------------------------------------------------ // Version:|Author: | Date: | Comment: // --------|--------|--------|-------------------------------------------------- +// 1.11 |jaswamin|07/22/14| Fixed the address // 1.7 |jaswmain|03/26/13| Removed DOS line endings // 1.6 |jaswamin|03/25/13| Removed 64 bit fir clearing function. // 1.5 |varkeykv|03/20/13| Additional moved FIR functions from clear firs to training files diff --git a/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C b/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C index 7c09e4a88..4e227ef7f 100644 --- a/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C +++ b/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ +/* Contributors Listed Below - COPYRIGHT 2012,2015 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -22,7 +22,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_cen_framelock.C,v 1.27 2014/06/01 16:20:59 baysah Exp $ +// $Id: proc_cen_framelock.C,v 1.29 2015/01/08 16:04:52 bwieman Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_cen_framelock.C,v $ //------------------------------------------------------------------------------ // *| @@ -40,6 +40,10 @@ // Change Log // Version | who |Date | Comment // ----------------------------------------------------------------------------- +// | | | +// 1.29 | bwieman |08-jan-14| revert of 1.28 +// 1.28 | baysah |12-DEC-14| Masked MCIFIR(26) MCIFIRQ_POWERBUS_PROTOCOL_ERROR due to CAPI defect HW281374 +// | | | // 1.27 | baysah |09-MAY-14| Added Delay in status register polling routine // | | | // 1.25 | baysah |11-APR-14| Changed MBI internal scom FIRs from masked to recoverable error per Marc Gollub @@ -2078,7 +2082,7 @@ fapi::ReturnCode proc_cen_framelock_cloned(const fapi::Target& i_pu_target, l_ecmdRc |= mci_data.setBit(23); //Replay Buffer Overrun l_ecmdRc |= mci_data.setBit(24); //Recoverable MC Internal Error l_ecmdRc |= mci_data.setBit(25); //Non-Recoverable MC Internal Error (xstop) - l_ecmdRc |= mci_data.setBit(26); //PowerBus Protocol Error (xstop) + l_ecmdRc |= mci_data.setBit(26); //PowerBus Protocol Error (xstop) //1.29 UNDONE Mask for CAPI defect HW281374 l_ecmdRc |= mci_data.setBit(27); //MCS Command List Timeout due to PB l_ecmdRc |= mci_data.setBit(28); //Multiple RCMD or CRESP active l_ecmdRc |= mci_data.setBit(29); //Inband Bar Hit with Incorrect TTYPE (xstop) @@ -2118,7 +2122,7 @@ fapi::ReturnCode proc_cen_framelock_cloned(const fapi::Target& i_pu_target, l_ecmdRc |= mci_data.clearBit(23); //Replay Buffer Overrun l_ecmdRc |= mci_data.clearBit(24); //Recoverable MC Internal Error l_ecmdRc |= mci_data.clearBit(25); //Non-Recoverable MC Internal Error (xstop) - l_ecmdRc |= mci_data.clearBit(26); //PowerBus Protocol Error (xstop) + l_ecmdRc |= mci_data.clearBit(26); //PowerBus Protocol Error (xstop) //1.29 UNDONE Mask for CAPI defect HW281374 l_ecmdRc |= mci_data.clearBit(27); //MCS Command List Timeout due to PB l_ecmdRc |= mci_data.clearBit(28); //Multiple RCMD or CRESP active l_ecmdRc |= mci_data.clearBit(29); //Inband Bar Hit with Incorrect TTYPE (xstop) diff --git a/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile b/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile index 843606996..b7b5e5beb 100755 --- a/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile +++ b/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile @@ -1,4 +1,4 @@ -#-- $Id: cen_ddrphy.initfile,v 1.33 2014/05/14 21:04:08 asaetow Exp $ +#-- $Id: cen_ddrphy.initfile,v 1.35 2014/05/28 14:46:21 asaetow Exp $ #-- $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/ #-- centaur/working/procedures/ec_ind/scoms/cen_ddrphy.initfile,v $ # @@ -6,6 +6,9 @@ #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- +# 1.35 |asaetow |05/28/14| Removed v1.34 from working since we will not be GAing with those settings. +# | | | NOTE: Re-evaluation in progress on PLL settings for SP1. +# 1.34 |asaetow |05/22/14| Changed ADR/DP18 PLL charge pump setting from 33x3=99uA to 66x2=132uA. Based on Qual FA sample data's potential DTMOAT leakage suspect Lot7DVBT. # 1.33 |asaetow |05/14/14| Changed ADR/DP18 VCO bit61 from 0b1 to 0b0 and PLL_TUNEF bit54 from 0b1 to 0b0 to dampen noise. Based on Qual FA sample data. # | | | Note bit61 is VCO low range from >700MHz to <700MHz. # | | | Note bit54 is Cap from 2.5pF to 1.0pF. diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_bulk_pwr_throttles.xml b/src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_bulk_pwr_throttles.xml index 958a9bad9..600e0c49b 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_bulk_pwr_throttles.xml +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_bulk_pwr_throttles.xml @@ -5,7 +5,9 @@ - + + + @@ -21,7 +23,7 @@ - + -- cgit v1.2.1