From c38096d4860780fe13c82978c1c9083d97767fcd Mon Sep 17 00:00:00 2001
From: Joe McGill <jmcgill@us.ibm.com>
Date: Sat, 23 Jul 2016 06:54:00 -0500
Subject: scan HWP updates

  tested via Cronus platform putring implementation

  p9_sbe_attr_setup
  p9_setup_sbe_config
    adjust mailbox write/read logic to properly handle cache contained mode

  p9_sbe_gptr_time_initf
    remove unused MC mc_iom[01|23]_time rings
    add OBUS1/2 scans
    add PCI pci[0|1|2]_pll_gptr rings
    add N2 n2_psi_gptr ring

  p9_sbe_repr_initf
    remove unused MC mc_iom[01|23]_repr rings
    add OBUS1/2 scans

  p9_sbe_nest_initf
    skip MC iom[01|23]_fure scans which require DETERMINISTIC_TEST_EN

  p9_sbe_io_initf
    skip PCI pci[0|1|2]_fure scans which require DETERMINISTIC_TEST_EN
    remove DETERMINISTIC_TEST_EN application for XB

  p9_hcd_cache_initf
    remove explicit initfile invocation/ring caching in wrapper
    correct putring targeting
    add EX ex_l2_mode ring scan

  p9_hcd_core_initf
    remove explicit initfile invocation/ring caching in wrapper
    add EC ec_mode ring scan

  add DBG/ERR trace for all putRing calls
  remove unused *gptr_time_repr_initf HWPs and wrappers

Change-Id: If1f8e9f5b327a6ab4f9b5271c53616ad20163b93
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27400
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-by: Kevin F. Reick <reick@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27402
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
---
 .../p9/procedures/hwp/perv/p9_mem_pll_initf.C      |  6 +++-
 .../p9/procedures/hwp/perv/p9_setup_sbe_config.C   | 42 +++++++++++++++++++---
 2 files changed, 43 insertions(+), 5 deletions(-)

diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_mem_pll_initf.C b/src/import/chips/p9/procedures/hwp/perv/p9_mem_pll_initf.C
index ea1cee8db..a159086f7 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_mem_pll_initf.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_mem_pll_initf.C
@@ -58,18 +58,22 @@ fapi2::ReturnCode p9_mem_pll_initf(const fapi2::Target<fapi2::TARGET_TYPE_PROC_C
             switch (l_mss_freq)
             {
                 case fapi2::ENUM_ATTR_MSS_FREQ_MT1866:
+                    FAPI_DBG("Scan mc_pll_bndy_bucket_1 ring");
                     l_ring_id = mc_pll_bndy_bucket_1;
                     break;
 
                 case fapi2::ENUM_ATTR_MSS_FREQ_MT2133:
+                    FAPI_DBG("Scan mc_pll_bndy_bucket_2 ring");
                     l_ring_id = mc_pll_bndy_bucket_2;
                     break;
 
                 case fapi2::ENUM_ATTR_MSS_FREQ_MT2400:
+                    FAPI_DBG("Scan mc_pll_bndy_bucket_3 ring");
                     l_ring_id = mc_pll_bndy_bucket_3;
                     break;
 
                 case fapi2::ENUM_ATTR_MSS_FREQ_MT2666:
+                    FAPI_DBG("Scan mc_pll_bndy_bucket_4 ring");
                     l_ring_id = mc_pll_bndy_bucket_4;
                     break;
 
@@ -82,7 +86,7 @@ fapi2::ReturnCode p9_mem_pll_initf(const fapi2::Target<fapi2::TARGET_TYPE_PROC_C
             }
 
             FAPI_TRY(fapi2::putRing(l_mcbist_target, l_ring_id, fapi2::RING_MODE_SET_PULSE_NSL),
-                     "Error from putRing");
+                     "Error from putRing (mc_pll_bndy, ringID: %d)", l_ring_id);
         }
     }
     else
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C b/src/import/chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C
index 0fbcbf149..97e4c6e7b 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C
@@ -177,14 +177,48 @@ fapi2::ReturnCode p9_setup_sbe_config(const
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYS_FORCE_ALL_CORES, FAPI_SYSTEM,
                                l_read_3));
 
-        l_read_scratch_reg.writeBit<0>(l_read_1.getBit<7>());
-        l_read_scratch_reg.writeBit<1>(l_read_3.getBit<7>());
-        l_read_scratch_reg.writeBit<2>(l_read_2.getBit<7>());
+        // set cache contained flag
+        if (l_read_1 == fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_CACHE_CONTAINED)
+        {
+            l_read_scratch_reg.setBit<0>();
+        }
+        else
+        {
+            l_read_scratch_reg.clearBit<0>();
+        }
+
+        // set all cores flag
+        if (l_read_3)
+        {
+            l_read_scratch_reg.setBit<1>();
+        }
+        else
+        {
+            l_read_scratch_reg.clearBit<1>();
+        }
+
+        // set risk level flag
+        if (l_read_2 == fapi2::ENUM_ATTR_RISK_LEVEL_TRUE)
+        {
+            l_read_scratch_reg.setBit<2>();
+        }
+        else
+        {
+            l_read_scratch_reg.clearBit<2>();
+        }
 
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_DISABLE_HBBL_VECTORS, FAPI_SYSTEM,
                                l_read_1));
 
-        l_read_scratch_reg.writeBit<3>(l_read_1.getBit<7>());
+        // set disable of HBBL exception vector flag
+        if (l_read_1 == fapi2::ENUM_ATTR_DISABLE_HBBL_VECTORS_TRUE)
+        {
+            l_read_scratch_reg.setBit<3>();
+        }
+        else
+        {
+            l_read_scratch_reg.clearBit<3>();
+        }
 
         FAPI_DBG("Setting up value of Scratch_reg5");
         //Setting SCRATCH_REGISTER_5 register value
-- 
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