From 90a1f442e0560ac159e34042cfbed558549e7b6a Mon Sep 17 00:00:00 2001 From: Stephen Cprek Date: Fri, 9 Aug 2013 16:12:28 -0500 Subject: Added defaults to attributes where none was specified Change-Id: I9e3c01cbfbb738eeb4dddd21fd92a6048e538481 RTC: 53049 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/5757 Tested-by: Jenkins Server Reviewed-by: Brian H. Horton Reviewed-by: A. Patrick Williams III --- src/usr/hwpf/hwp/memory_attributes.xml | 15 + .../targeting/common/xmltohb/attribute_types.xml | 309 ++++------------- .../common/xmltohb/attribute_types_hb.xml | 13 - .../common/xmltohb/simics_MURANO.system.xml | 208 ++++++++++-- .../common/xmltohb/simics_VENICE.system.xml | 373 ++++++++++++++++----- src/usr/targeting/common/xmltohb/target_types.xml | 22 +- .../targeting/common/xmltohb/vbu_MURANO.system.xml | 176 ++++++++++ .../targeting/common/xmltohb/vbu_VENICE.system.xml | 129 ++++++- 8 files changed, 872 insertions(+), 373 deletions(-) diff --git a/src/usr/hwpf/hwp/memory_attributes.xml b/src/usr/hwpf/hwp/memory_attributes.xml index 1f140743a..af1fb78d3 100644 --- a/src/usr/hwpf/hwp/memory_attributes.xml +++ b/src/usr/hwpf/hwp/memory_attributes.xml @@ -3161,6 +3161,21 @@ Firmware shares some code with the processor, so the attribute is named so they + + ATTR_CDIMM_SENSOR_MAP_PRIMARY TARGET_TYPE_MEMBUF_CHIP diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml index 35aea2402..2573a3de9 100644 --- a/src/usr/targeting/common/xmltohb/attribute_types.xml +++ b/src/usr/targeting/common/xmltohb/attribute_types.xml @@ -317,7 +317,6 @@ Scratch attribute that can be used for dev/test - 0 volatile-zeroed @@ -334,7 +333,6 @@ Scratch attribute that can be used for dev/test - 0 volatile-zeroed @@ -351,7 +349,6 @@ Scratch attribute that can be used for dev/test - 0 volatile-zeroed @@ -368,7 +365,6 @@ Scratch attribute that can be used for dev/test - 0 volatile-zeroed @@ -385,7 +381,6 @@ Scratch attribute that can be used for dev/test - 0 volatile-zeroed @@ -402,7 +397,6 @@ Scratch attribute that can be used for dev/test - 0 volatile-zeroed @@ -419,7 +413,6 @@ Scratch attribute that can be used for dev/test - 0 32 @@ -437,7 +430,6 @@ Scratch attribute that can be used for dev/test - 0 2, 3, 4 @@ -455,7 +447,6 @@ Scratch attribute that can be used for dev/test - 0 8 @@ -473,7 +464,6 @@ Scratch attribute that can be used for dev/test - 0 2,3 @@ -491,7 +481,6 @@ Scratch attribute that can be used for dev/test - 0 4 @@ -509,7 +498,6 @@ Scratch attribute that can be used for dev/test - 0 2,2 @@ -569,7 +557,6 @@ Dummy attribute on the heap with zero initialization - 5 volatile-zeroed @@ -1165,7 +1152,6 @@ attribute indicating the chip target's EC level - 0 volatile-zeroed @@ -1182,7 +1168,6 @@ attribute indicating the chip's ID - 0 volatile-zeroed @@ -1211,7 +1196,6 @@ L2 tier0 read epsilon register value. - 0 volatile-zeroed @@ -1228,7 +1212,6 @@ L2 tier1 read epsilon register value. - 0 volatile-zeroed @@ -1245,7 +1228,6 @@ L2 tier2 read epsilon register value. - 0 volatile-zeroed @@ -1262,7 +1244,6 @@ L2 force tier2 read epsilon protect (all tiers). - 0 volatile-zeroed @@ -1279,7 +1260,6 @@ L2 write epsilon register value. - 0 volatile-zeroed @@ -1296,7 +1276,6 @@ L3 tier0 read epsilon register value. - 0 volatile-zeroed @@ -1313,7 +1292,6 @@ L3 tier1 read epsilon register value. - 0 volatile-zeroed @@ -1330,7 +1308,6 @@ L3 tier2 read epsilon register value. - 0 volatile-zeroed @@ -1347,7 +1324,6 @@ L3 force tier2 read epsilon protect (all tiers). - 0 volatile-zeroed @@ -1364,7 +1340,6 @@ L3 write epsilon register value. - 0 volatile-zeroed @@ -2532,7 +2507,6 @@ Base Address for all mainstore behind this processor - 0 volatile-zeroed @@ -2549,7 +2523,6 @@ Base Address for all mirrored mainstore behind this processor - 0 volatile-zeroed @@ -3440,13 +3413,16 @@ Selects which voltage level to place the Core and ECO domain PFETs upon Winkle e + PM_PFET_POWERUP_CORE_DELAY0 PROC_CHIP Attribute - + + 0 + non-volatile @@ -3456,13 +3432,16 @@ Selects which voltage level to place the Core and ECO domain PFETs upon Winkle e + PM_PFET_POWERUP_CORE_DELAY1 PROC_CHIP Attribute - + + 0 + non-volatile @@ -3527,13 +3506,16 @@ Selects which voltage level to place the Core and ECO domain PFETs upon Winkle e + PM_PFET_POWERDOWN_CORE_DELAY0 PROC_CHIP Attribute - + + 0 + non-volatile @@ -3543,13 +3525,16 @@ Selects which voltage level to place the Core and ECO domain PFETs upon Winkle e + PM_PFET_POWERDOWN_CORE_DELAY1 PROC_CHIP Attribute - + + 0 + non-volatile @@ -3614,13 +3599,16 @@ Selects which voltage level to place the Core and ECO domain PFETs upon Winkle e + PM_PFET_POWERUP_ECO_DELAY0 PROC_CHIP Attribute - + + 0 + non-volatile @@ -3630,13 +3618,16 @@ Selects which voltage level to place the Core and ECO domain PFETs upon Winkle e + PM_PFET_POWERUP_ECO_DELAY1 PROC_CHIP Attribute - + + 0 + non-volatile @@ -3701,13 +3692,16 @@ Selects which voltage level to place the Core and ECO domain PFETs upon Winkle e + PM_PFET_POWERDOWN_ECO_DELAY0 PROC_CHIP Attribute - + + 0 + non-volatile @@ -3717,13 +3711,16 @@ Selects which voltage level to place the Core and ECO domain PFETs upon Winkle e + PM_PFET_POWERDOWN_ECO_DELAY1 PROC_CHIP Attribute - + + 0 + non-volatile @@ -4366,7 +4363,9 @@ Divider for the 1us PBAX hang pulse. A hang is detected after two divided hang Provided by the Machine Readable Workbook. - + + 0 + non-volatile @@ -4399,6 +4398,7 @@ Divider for the 1us PBAX hang pulse. A hang is detected after two divided hang + PM_SPIVID_PORT_ENABLE @@ -5644,7 +5644,7 @@ firmware notes: Used as override attribute for pstate procedure 32 - volatile + volatile-zeroed @@ -5723,7 +5723,9 @@ firmware notes: Used as override attribute for pstate procedure 64-bit address representing BAR RA - + + 0x0000000000000000 + non-volatile @@ -5763,7 +5765,10 @@ firmware notes: Used as override attribute for pstate procedure mask applied to RA 14:43 - + + + 0x0000000004000000 + non-volatile @@ -5802,7 +5807,9 @@ firmware notes: Used as override attribute for pstate procedure 64-bit address representing BAR RA - + + 0x0000000000000000 + non-volatile @@ -5853,7 +5860,10 @@ firmware notes: Used as override attribute for pstate procedure mask applied to RA 14:43 - + + + 0x0000000004000000 + non-volatile @@ -5872,7 +5882,9 @@ firmware notes: Used as override attribute for pstate procedure 64-bit address representing BAR RA - + + 0x0000000000000000 + non-volatile @@ -5891,7 +5903,10 @@ firmware notes: Used as override attribute for pstate procedure mask applied to RA 14:43 - + + + 0x0000000004000000 + non-volatile @@ -5911,7 +5926,9 @@ firmware notes: Used as override attribute for pstate procedure 64-bit proc_sbe_security_setup_vector - + + 0x0000000000000000 + non-volatile @@ -5928,7 +5945,6 @@ firmware notes: Used as override attribute for pstate procedure DRAM Voltage. Initialized and used by HWPs. - 0 volatile-zeroed @@ -5945,7 +5961,6 @@ firmware notes: Used as override attribute for pstate procedure Frequency of memory channel in MHz. Initialized and used by HWPs. - 0 volatile-zeroed @@ -5962,7 +5977,6 @@ firmware notes: Used as override attribute for pstate procedure DIMM Manufacturer ID Code. Initialized and used by HWPs. - 0 2,2 @@ -5980,7 +5994,6 @@ firmware notes: Used as override attribute for pstate procedure DIMM ranks configured. Initialized and used by HWPs. - 0 2,2 @@ -5998,7 +6011,6 @@ firmware notes: Used as override attribute for pstate procedure Number of ranks per DIMM. Initialized and used by HWPs. - 0 2,2 @@ -6016,7 +6028,6 @@ firmware notes: Used as override attribute for pstate procedure Type of DIMM. Initialized and used by HWPs. - 0 volatile-zeroed @@ -6033,7 +6044,6 @@ firmware notes: Used as override attribute for pstate procedure DIMM is a custom DIMM. Sometimes this is known as a CDIMM, but technically, we could support Custom DIMMs of different types than an UDIMM, such as RDIMM and LRDIMM. Created in mss_eff_cnfg - 0 volatile-zeroed @@ -6050,7 +6060,6 @@ firmware notes: Used as override attribute for pstate procedure DRAM Device Width. Initialized and used by HWPs. - 0 volatile-zeroed @@ -6067,7 +6076,6 @@ firmware notes: Used as override attribute for pstate procedure DRAM Generation. Initialized and used by HWPs. - 0 volatile-zeroed @@ -6084,7 +6092,6 @@ firmware notes: Used as override attribute for pstate procedure Primary RankGroup0. Initialized and used by HWPs. - 0 2 @@ -6102,7 +6109,6 @@ firmware notes: Used as override attribute for pstate procedure Primary RankGroup1. Initialized and used by HWPs. - 0 2 @@ -6120,7 +6126,6 @@ firmware notes: Used as override attribute for pstate procedure Primary RankGroup2. Initialized and used by HWPs. - 0 2 @@ -6138,7 +6143,6 @@ firmware notes: Used as override attribute for pstate procedure Primary RankGroup3. Initialized and used by HWPs. - 0 2 @@ -6156,7 +6160,6 @@ firmware notes: Used as override attribute for pstate procedure Secondary RankGroup0. Initialized and used by HWPs. - 0 2 @@ -6174,7 +6177,6 @@ firmware notes: Used as override attribute for pstate procedure Secondary RankGroup1. Initialized and used by HWPs. - 0 2 @@ -6192,7 +6194,6 @@ firmware notes: Used as override attribute for pstate procedure Secondary RankGroup2. Initialized and used by HWPs. - 0 2 @@ -6210,7 +6211,6 @@ firmware notes: Used as override attribute for pstate procedure Secondary RankGroup3. Initialized and used by HWPs. - 0 2 @@ -6228,7 +6228,6 @@ firmware notes: Used as override attribute for pstate procedure Tertiary RankGroup0. Initialized and used by HWPs. - 0 2 @@ -6246,7 +6245,6 @@ firmware notes: Used as override attribute for pstate procedure Tertiary RankGroup1. Initialized and used by HWPs. - 0 2 @@ -6264,7 +6262,6 @@ firmware notes: Used as override attribute for pstate procedure Tertiary RankGroup2. Initialized and used by HWPs. - 0 2 @@ -6282,7 +6279,6 @@ firmware notes: Used as override attribute for pstate procedure Tertiary RankGroup3. Initialized and used by HWPs. - 0 2 @@ -6300,7 +6296,6 @@ firmware notes: Used as override attribute for pstate procedure Quaternary RankGroup0. Initialized and used by HWPs. - 0 2 @@ -6318,7 +6313,6 @@ firmware notes: Used as override attribute for pstate procedure Quaternary RankGroup1. Initialized and used by HWPs. - 0 2 @@ -6336,7 +6330,6 @@ firmware notes: Used as override attribute for pstate procedure Quaternary RankGroup2. Initialized and used by HWPs. - 0 2 @@ -6354,7 +6347,6 @@ firmware notes: Used as override attribute for pstate procedure Quaternary RankGroup3. Initialized and used by HWPs. - 0 2 @@ -6376,7 +6368,6 @@ firmware notes: Used as override attribute for pstate procedure Rank Read ODT. Initialized and used by HWPs. - 0 2,2,4 @@ -6394,7 +6385,6 @@ firmware notes: Used as override attribute for pstate procedure Rank Write ODT. Initialized and used by HWPs. - 0 2,2,4 @@ -6412,7 +6402,6 @@ firmware notes: Used as override attribute for pstate procedure DRAM Ron. Initialized and used by HWPs. - 0 2,2 @@ -6430,7 +6419,6 @@ firmware notes: Used as override attribute for pstate procedure DRAM Rtt_Nom. Initialized and used by HWPs. - 0 2,2,4 @@ -6448,7 +6436,6 @@ firmware notes: Used as override attribute for pstate procedure DRAM Rtt_WR. Initialized and used by HWPs. - 0 2,2,4 @@ -6466,7 +6453,6 @@ firmware notes: Used as override attribute for pstate procedure DRAM Write Vref. Initialized and used by HWPs. - 0 2 @@ -6484,7 +6470,6 @@ firmware notes: Used as override attribute for pstate procedure DRAM Write Vref for DDR4. Initialized and used by HWPs. - 0 2 @@ -6502,7 +6487,6 @@ firmware notes: Used as override attribute for pstate procedure Centaur DQ and DQS Drive Impedance. Initialized and used by HWPs. - 0 2 @@ -6520,7 +6504,6 @@ firmware notes: Used as override attribute for pstate procedure Centaur Address Drive Impedance. Initialized and used by HWPs. - 0 2 @@ -6538,7 +6521,6 @@ firmware notes: Used as override attribute for pstate procedure Centaur Control Drive Impedance. Initialized and used by HWPs. - 0 2 @@ -6556,7 +6538,6 @@ firmware notes: Used as override attribute for pstate procedure Centaur Clock Drive Impedance. Initialized and used by HWPs. - 0 2 @@ -6574,7 +6555,6 @@ firmware notes: Used as override attribute for pstate procedure Centaur Spare Clock Drive Impedance. Initialized and used by HWPs. - 0 2 @@ -6592,7 +6572,6 @@ firmware notes: Used as override attribute for pstate procedure Centaur DQ and DQS Receiver Impedance. Initialized and used by HWPs. - 0 2 @@ -6610,7 +6589,6 @@ firmware notes: Used as override attribute for pstate procedure Centaur DQ and DQS Slew Rate. Initialized and used by HWPs. - 0 2 @@ -6628,7 +6606,6 @@ firmware notes: Used as override attribute for pstate procedure Centaur Address Slew Rate. Initialized and used by HWPs. - 0 2 @@ -6646,7 +6623,6 @@ firmware notes: Used as override attribute for pstate procedure Centaur Clock Slew Rate. Initialized and used by HWPs. - 0 2 @@ -6664,7 +6640,6 @@ firmware notes: Used as override attribute for pstate procedure Centaur Spare Clock Slew Rate. Initialized and used by HWPs. - 0 2 @@ -6682,7 +6657,6 @@ firmware notes: Used as override attribute for pstate procedure Centaur Control Slew Rate. Initialized and used by HWPs. - 0 2 @@ -6700,7 +6674,6 @@ firmware notes: Used as override attribute for pstate procedure Centaur Read Vref. Initialized and used by HWPs. - 0 2 @@ -6720,7 +6693,6 @@ firmware notes: Used as override attribute for pstate procedure Enables for which impedance values can be used and tested in a timing test. Initialized and used by HWPs. - 0 2 @@ -6738,7 +6710,6 @@ firmware notes: Used as override attribute for pstate procedure Enables for which impedance values can be used and tested in a timing test. Initialized and used by HWPs. - 0 2 @@ -6756,7 +6727,6 @@ firmware notes: Used as override attribute for pstate procedure Enables for which impedance values can be used and tested in a timing test. Initialized and used by HWPs. - 0 2 @@ -6774,7 +6744,6 @@ firmware notes: Used as override attribute for pstate procedure Enables for which impedance values can be used and tested in a timing test. Initialized and used by HWPs. - 0 2 @@ -6792,7 +6761,6 @@ firmware notes: Used as override attribute for pstate procedure Enables for which impedance values can be used and tested in a timing test. Initialized and used by HWPs. - 0 2 @@ -6810,7 +6778,6 @@ firmware notes: Used as override attribute for pstate procedure Slew Rates that can be selected during timing adjustments. Initialized and used by HWPs. - 0 2 @@ -6828,7 +6795,6 @@ firmware notes: Used as override attribute for pstate procedure Slew Rates that can be selected during timing adjustments. Initialized and used by HWPs. - 0 2 @@ -6846,7 +6812,6 @@ firmware notes: Used as override attribute for pstate procedure Slew Rates that can be selected during timing adjustments. Initialized and used by HWPs. - 0 2 @@ -6864,7 +6829,6 @@ firmware notes: Used as override attribute for pstate procedure Slew Rates that can be selected during timing adjustments. Initialized and used by HWPs. - 0 2 @@ -6882,7 +6846,6 @@ firmware notes: Used as override attribute for pstate procedure Slew Rates that can be selected during timing adjustments. Initialized and used by HWPs. - 0 2 @@ -6900,7 +6863,6 @@ firmware notes: Used as override attribute for pstate procedure Enables for which VREF to use on the WR Schmoo. Initialized and used by HWPs. - 0 2 @@ -6918,7 +6880,6 @@ firmware notes: Used as override attribute for pstate procedure Enables for which VREF to use on the WR Schmoo for DDR4. Initialized and used by HWPs. - 0 2 @@ -6936,7 +6897,6 @@ firmware notes: Used as override attribute for pstate procedure Enables for which VREF value can be used in timing adjustments. Initialized and used by HWPs. - 0 2 @@ -6954,7 +6914,6 @@ firmware notes: Used as override attribute for pstate procedure DIMM Size. Initialized and used by HWPs. - 0 2,2 @@ -6972,7 +6931,6 @@ firmware notes: Used as override attribute for pstate procedure Number of DRAM banks. Initialized and used by HWPs. - 0 volatile-zeroed @@ -6989,7 +6947,6 @@ firmware notes: Used as override attribute for pstate procedure Number of DRAM rows. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7006,7 +6963,6 @@ firmware notes: Used as override attribute for pstate procedure Number of DRAM columns. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7023,7 +6979,6 @@ firmware notes: Used as override attribute for pstate procedure DRAM Density. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7040,7 +6995,6 @@ firmware notes: Used as override attribute for pstate procedure DRAM RAS to CAS Delay. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7057,7 +7011,6 @@ firmware notes: Used as override attribute for pstate procedure DRAM Row ACT to Row ACT Delay. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7074,7 +7027,6 @@ firmware notes: Used as override attribute for pstate procedure DRAM Row Precharge Delay. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7091,7 +7043,6 @@ firmware notes: Used as override attribute for pstate procedure DRAM ACT to Precharge Delay. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7108,7 +7059,6 @@ firmware notes: Used as override attribute for pstate procedure DRAM ACT to ACT/Refresh Delay. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7125,7 +7075,6 @@ firmware notes: Used as override attribute for pstate procedure Refresh Interval. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7142,7 +7091,6 @@ firmware notes: Used as override attribute for pstate procedure DRAM Refresh Recovery Delay. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7159,7 +7107,6 @@ firmware notes: Used as override attribute for pstate procedure DRAM Internal Write to Read Delay. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7176,7 +7123,6 @@ firmware notes: Used as override attribute for pstate procedure DRAM Internal Read to Precharge Delay. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7193,7 +7139,6 @@ firmware notes: Used as override attribute for pstate procedure DRAM Four ACT Window Delay. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7210,7 +7155,6 @@ firmware notes: Used as override attribute for pstate procedure DRAM Burst Length. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7227,7 +7171,6 @@ firmware notes: Used as override attribute for pstate procedure DRAM CAS Latency. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7244,7 +7187,6 @@ firmware notes: Used as override attribute for pstate procedure DRAM Additive Latency. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7261,7 +7203,6 @@ firmware notes: Used as override attribute for pstate procedure DRAM CAS Write Latency. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7278,7 +7219,6 @@ firmware notes: Used as override attribute for pstate procedure DRAM Read Burst Type. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7295,7 +7235,6 @@ firmware notes: Used as override attribute for pstate procedure DRAM Test Mode. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7312,7 +7251,6 @@ firmware notes: Used as override attribute for pstate procedure DRAM DLL Reset. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7329,7 +7267,6 @@ firmware notes: Used as override attribute for pstate procedure DRAM Write Recovery. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7346,7 +7283,6 @@ firmware notes: Used as override attribute for pstate procedure DRAM DLL Precharge PD. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7363,7 +7299,6 @@ firmware notes: Used as override attribute for pstate procedure DRAM DLL Enable. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7380,7 +7315,6 @@ firmware notes: Used as override attribute for pstate procedure DRAM TDQS. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7397,7 +7331,6 @@ firmware notes: Used as override attribute for pstate procedure DRAM Write Level Enable. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7414,7 +7347,6 @@ firmware notes: Used as override attribute for pstate procedure DRAM output buffer. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7431,7 +7363,6 @@ firmware notes: Used as override attribute for pstate procedure DRAM Partial Array Self-Refresh. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7448,7 +7379,6 @@ firmware notes: Used as override attribute for pstate procedure DRAM Auto Self-Refresh. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7465,7 +7395,6 @@ firmware notes: Used as override attribute for pstate procedure DRAM Self-Refresh Temperature Range. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7482,7 +7411,6 @@ firmware notes: Used as override attribute for pstate procedure Multi Purpose Register Location. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7499,7 +7427,6 @@ firmware notes: Used as override attribute for pstate procedure Multi Purpose Register Mode. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7516,7 +7443,6 @@ firmware notes: Used as override attribute for pstate procedure DIMM RCD Control Word. Initialized and used by HWPs. - 0 2,2 @@ -7534,7 +7460,6 @@ firmware notes: Used as override attribute for pstate procedure DIMM RCD IBT. Initialized and used by HWPs. - 0 2,2 @@ -7552,7 +7477,6 @@ firmware notes: Used as override attribute for pstate procedure DIMM RCD Mirror mode. Initialized and used by HWPs. - 0 2,2 @@ -7570,7 +7494,6 @@ firmware notes: Used as override attribute for pstate procedure Specifies the schmoo mode to use during draminit_train_adv. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7587,7 +7510,6 @@ firmware notes: Used as override attribute for pstate procedure Specifies the schmoo mode to use during draminit_train_adv. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7604,7 +7526,6 @@ firmware notes: Used as override attribute for pstate procedure Specifies the schmoo test to run during draminit_train_adv. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7621,7 +7542,6 @@ firmware notes: Used as override attribute for pstate procedure Specifies the schmoo parameters to use during draminit_train_adv. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7638,7 +7558,6 @@ firmware notes: Used as override attribute for pstate procedure Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory. - 0 volatile-zeroed @@ -7655,7 +7574,6 @@ firmware notes: Used as override attribute for pstate procedure Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory. - 0 volatile-zeroed @@ -7672,7 +7590,6 @@ firmware notes: Used as override attribute for pstate procedure Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory. - 0 volatile-zeroed @@ -7689,7 +7606,6 @@ firmware notes: Used as override attribute for pstate procedure Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory. - 0 volatile-zeroed @@ -7706,7 +7622,6 @@ firmware notes: Used as override attribute for pstate procedure Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory. - 0 volatile-zeroed @@ -7723,7 +7638,6 @@ firmware notes: Used as override attribute for pstate procedure Specifies the memcal interval in clocks. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7740,7 +7654,6 @@ firmware notes: Used as override attribute for pstate procedure Specifies the zqcal interval in clocks. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7757,7 +7670,6 @@ firmware notes: Used as override attribute for pstate procedure Specifies the memory topology type. Initialized and used by HWPs. - 0 2,2 @@ -7775,7 +7687,6 @@ firmware notes: Used as override attribute for pstate procedure Specifies the number of DIMM dimensions that are valid per port. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7792,7 +7703,6 @@ firmware notes: Used as override attribute for pstate procedure Specifies the DRAM package type. Initialized and used by HWPs. - 0 2,2 @@ -7810,7 +7720,6 @@ firmware notes: Used as override attribute for pstate procedure Specifies the number of master ranks per DIMM. Initialized and used by HWPs. - 0 2,2 @@ -7828,7 +7737,6 @@ firmware notes: Used as override attribute for pstate procedure Specifies the number of DRAM packages per rank. Initialized and used by HWPs. - 0 2,2 @@ -7846,7 +7754,6 @@ firmware notes: Used as override attribute for pstate procedure Specifies the number of DRAM dies per package. Initialized and used by HWPs. - 0 2,2 @@ -7864,7 +7771,6 @@ firmware notes: Used as override attribute for pstate procedure DIMM throttle numerator. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7881,7 +7787,6 @@ firmware notes: Used as override attribute for pstate procedure DIMM throttle denominator. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7898,7 +7803,6 @@ firmware notes: Used as override attribute for pstate procedure This is the throttle numerator setting for cfg_nm_n_per_chip. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7915,7 +7819,6 @@ firmware notes: Used as override attribute for pstate procedure Channel total memory watts. Initialized and used by HWPs. - 0 volatile-zeroed @@ -7932,7 +7835,6 @@ firmware notes: Used as override attribute for pstate procedure DIMM Power slope value. Initialized and used by HWPs. - 0 2,2 @@ -7950,7 +7852,6 @@ firmware notes: Used as override attribute for pstate procedure DIMM Power slope value. Initialized and used by HWPs. - 0 2,2 @@ -7968,7 +7869,6 @@ firmware notes: Used as override attribute for pstate procedure DIMM Power intercept value. Initialized and used by HWPs. - 0 2,2 @@ -7986,7 +7886,6 @@ firmware notes: Used as override attribute for pstate procedure DIMM Power intercept value. Initialized and used by HWPs. - 0 2,2 @@ -8004,7 +7903,6 @@ firmware notes: Used as override attribute for pstate procedure DIMM Max Bandwidth in GBs. Initialized and used by HWPs. - 0 2,2 @@ -8022,7 +7920,6 @@ firmware notes: Used as override attribute for pstate procedure DIMM Max Bandwidth in MRs. Initialized and used by HWPs. - 0 2,2 @@ -8040,7 +7937,6 @@ firmware notes: Used as override attribute for pstate procedure Channel Max Bandwidth in GBs. Initialized and used by HWPs. - 0 2 @@ -8058,7 +7954,6 @@ firmware notes: Used as override attribute for pstate procedure Channel Pair Max Bandwidth in GBs. Initialized and used by HWPs. - 0 2 @@ -8076,7 +7971,6 @@ firmware notes: Used as override attribute for pstate procedure Channel Max Bandwidth MRs. Initialized and used by HWPs. - 0 2 @@ -8094,7 +7988,6 @@ firmware notes: Used as override attribute for pstate procedure Channel Pair Max Bandwidth MRs. Initialized and used by HWPs. - 0 2 @@ -8112,7 +8005,6 @@ firmware notes: Used as override attribute for pstate procedure DIMM Max Power output. Initialized and used by HWPs. - 0 2,2 @@ -8130,7 +8022,6 @@ firmware notes: Used as override attribute for pstate procedure Channel Max Power output. Initialized and used by HWPs. - 0 2 @@ -8148,7 +8039,6 @@ firmware notes: Used as override attribute for pstate procedure Channel Pair Max Power output. Initialized and used by HWPs. - 0 volatile-zeroed @@ -8165,7 +8055,6 @@ firmware notes: Used as override attribute for pstate procedure Runtime throttle numerator setting for cfg_nm_n_per_mba. Initialized and used by HWPs. - 0 volatile-zeroed @@ -8182,7 +8071,6 @@ firmware notes: Used as override attribute for pstate procedure Runtime throttle denominator setting for cfg_nm_m. Initialized and used by HWPs. - 0 volatile-zeroed @@ -8199,7 +8087,6 @@ firmware notes: Used as override attribute for pstate procedure Runtime throttle numerator setting for cfg_nm_n_per_chip. Initialized and used by HWPs. - 0 volatile-zeroed @@ -8234,7 +8121,6 @@ firmware notes: Used as override attribute for pstate procedure Set by the platform depending on DD1 vs DD1.01. If true, then SI settings affected by the NWELL problem are adjusted. Used in eff_config - 0 volatile-zeroed @@ -8354,7 +8240,6 @@ firmware notes: Used as override attribute for pstate procedure override the default Centaur MEM PLL settings with user-specified scan chain data. 1 = ON, 0 = OFF. - 0 volatile-zeroed @@ -8371,7 +8256,6 @@ firmware notes: Used as override attribute for pstate procedure A 8 bit vector that would be a designation of which MC are involved in the group. Initialized and used by HWPs. - 0 8 @@ -8392,7 +8276,6 @@ firmware notes: Used as override attribute for pstate procedure Measured in GB - 0 16,16 @@ -8411,7 +8294,6 @@ Measured in GB This factors in functionality - 0 volatile-zeroed @@ -8436,7 +8318,6 @@ This factors in functionality bits6:7 will be consumed together to form COARSE_LVL. - 0 volatile-zeroed @@ -8453,7 +8334,6 @@ bits6:7 will be consumed together to form COARSE_LVL. A numerical number indicating if the memory procedures are complete. written by mss_setup_bars when the bars are now functional in the processor. - 0 volatile-zeroed @@ -8470,7 +8350,6 @@ bits6:7 will be consumed together to form COARSE_LVL. The 4 bit result of running the slew calibration algorithm at various rates and impedances - 0 2, 4, 4 @@ -8488,7 +8367,6 @@ bits6:7 will be consumed together to form COARSE_LVL. The 4 bit result of running the slew calibration algorithm at various rates and impedances - 0 2, 4, 4 @@ -8510,7 +8388,6 @@ bits6:7 will be consumed together to form COARSE_LVL. - 0 2 @@ -9335,7 +9212,6 @@ bits6:7 will be consumed together to form COARSE_LVL. Measured in GB - 0 16,16 @@ -9353,7 +9229,6 @@ Measured in GB Rank to CKE map. Used in various locations and is computed in mss_eff_cnfg_cke_map. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: mss_eff_cnfg_cke_map consumer: various firmware notes: none - 0 2,2,4 @@ -9371,7 +9246,6 @@ Measured in GB Rank to Spare CKE map. Used in various locations and is computed in mss_eff_cnfg_cke_map. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: mss_eff_cnfg_cke_map consumer: various firmware notes: none - 0 2,2,4 @@ -9389,7 +9263,6 @@ Measured in GB Spare DRAM availability. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: mss_eff_cnfg consumer: various firmware notes: load from spd - 0 2,2,4 @@ -9407,7 +9280,6 @@ Measured in GB Set by the centaur mss_get_cen_ecid function used diagnostic and chip characterization reporting - 0 volatile-zeroed @@ -9990,7 +9862,6 @@ Measured in GB - 0 2 @@ -10012,7 +9883,6 @@ Measured in GB - 0 2 @@ -10063,7 +9933,6 @@ Measured in GB - 0 volatile-zeroed @@ -10160,7 +10029,7 @@ Measured in GB - non-volatile + volatile-zeroed @@ -10327,7 +10196,6 @@ Measured in GB firmware notes: Platforms should initialize this attribute to AUTO (0) - 0 volatile-zeroed @@ -10345,7 +10213,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)Enables mcbist data pattern selection. - 0 volatile-zeroed @@ -10362,7 +10229,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)Enables mcbist test type selection. - 0 volatile-zeroed @@ -10379,7 +10245,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)MCBIST support for printing - 0 volatile-zeroed @@ -10396,7 +10261,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)MCBIST support for enabling data - 0 volatile-zeroed @@ -10413,7 +10277,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)MCBIST support for rank selection - 0 volatile-zeroed @@ -10430,7 +10293,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)MCBIST support for bank selection - 0 volatile-zeroed @@ -10447,7 +10309,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)MCBIST for multiple setup - 0 volatile-zeroed @@ -10464,7 +10325,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)Can choose mcbist address mode for full,half or quarter addressing mode. - 0 volatile-zeroed @@ -10481,7 +10341,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0) Defines the rank for the Mcbist - 0 volatile-zeroed @@ -10498,7 +10357,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)Defines the start address for the Mcbist address range - 0 volatile-zeroed @@ -10515,7 +10373,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)Defines the end address for the Mcbist address range - 0 volatile-zeroed @@ -10532,7 +10389,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)Enables error capture; basically a flag. - 0 volatile-zeroed @@ -10549,7 +10405,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)Define mcbist Max timeout - 0 volatile-zeroed @@ -10566,7 +10421,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)Enable which port prints are required. - 0 volatile-zeroed @@ -10583,7 +10437,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)Flag to stop Mcbist on Error. - 0 volatile-zeroed @@ -10600,7 +10453,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)Define data seed for the random data pattern or test - 0 volatile-zeroed @@ -10617,7 +10469,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)The address interleave map with user cases or deafult cases of BANK_RANK,RANK_BANK,BANK_ONLY,RANK_ONLYRANKS_DIMM0,RANKS_DIMM1,USER_PATTERN. - 0 volatile-zeroed @@ -10634,7 +10485,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)User defined constraint for limiting number of rows for addressing. - 0 volatile-zeroed @@ -10651,7 +10501,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)User defined constraint for limiting number of columns for addressing. - 0 volatile-zeroed @@ -10668,7 +10517,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)User defined constraint for limiting number of ranks for addressing. - 0 volatile-zeroed @@ -10685,7 +10533,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)User defined constraint for limiting number of banks for addressing. - 0 volatile-zeroed @@ -10702,7 +10549,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)If slave ranks exists;Restrict usage or enable addressing on them as well. - 0 volatile-zeroed @@ -10719,7 +10565,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)To Define custom addressing map ; Input by user. - 0 volatile-zeroed @@ -10736,7 +10581,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)Flag for Addressing to go sequential manner or random. - 0 volatile-zeroed @@ -10782,7 +10626,9 @@ firmware notes: Platforms should initialize this attribute to AUTO (0) - + + 0 + 64 non-volatile @@ -12464,7 +12310,7 @@ firmware notes: Platforms should initialize this attribute to AUTO (0) - 0x00 + volatile-zeroed @@ -12486,7 +12332,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0) - 0 volatile-zeroed @@ -12498,26 +12343,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0) - - MEMB_NEST_FREQ - - Frequency of the Centaur NEST PLL in MHz. - consumer: cen_mem_pll_initf - firmware notes: Platforms should initialize the attribute to the - correct value for the system. - - - - - volatile - - - - ATTR_MEMB_NEST_FREQ - DIRECT - - - CDIMM_SENSOR_MAP_PRIMARY @@ -12587,7 +12412,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0) - 0 2,2 @@ -12609,7 +12433,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0) - 0 volatile-zeroed diff --git a/src/usr/targeting/common/xmltohb/attribute_types_hb.xml b/src/usr/targeting/common/xmltohb/attribute_types_hb.xml index 208d2a5f0..85043526c 100644 --- a/src/usr/targeting/common/xmltohb/attribute_types_hb.xml +++ b/src/usr/targeting/common/xmltohb/attribute_types_hb.xml @@ -34,7 +34,6 @@ 1 = in Memory Preserving IPL mode. 0 = in normal IPL mode. - 0 volatile-zeroed @@ -52,7 +51,6 @@ Cached Virtual Address of Xscom memory space for this Chip - 0 volatile-zeroed @@ -66,7 +64,6 @@ Mutex for FSI Master Operations - 0 volatile-zeroed @@ -81,7 +78,6 @@ Host boot mutex for testing - 0 volatile-zeroed @@ -95,7 +91,6 @@ Mutex for I2C Master engine 0 - 0 volatile-zeroed @@ -109,7 +104,6 @@ Mutex for I2C Master engine 1 - 0 volatile-zeroed @@ -123,7 +117,6 @@ Mutex for I2C Master engine 2 - 0 volatile-zeroed @@ -137,7 +130,6 @@ Mutex for FSI-based SCOM Operations - 0 volatile-zeroed @@ -151,7 +143,6 @@ Mutex for Indirect SCOM read operation - 0 volatile-zeroed @@ -209,7 +200,6 @@ Cached Virtual Address of Inband Scom memory space for this Chip - 0 volatile-zeroed @@ -222,7 +212,6 @@ Mutex for Inband SCOM Operations - 0 volatile-zeroed @@ -235,7 +224,6 @@ Used to force IBSCOM enabled for lab testing - 0 volatile-zeroed @@ -250,7 +238,6 @@ --> - 0 volatile-zeroed diff --git a/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml b/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml index ab189c50b..61c47d4c6 100644 --- a/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml +++ b/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml @@ -214,6 +214,42 @@ 0b11 + MAX_EXS_PER_PROC_CHIP + 6 + + MAX_MCS_PER_SYSTEM + 16 + + X_EREPAIR_THRESHOLD_FIELD + 1 + + A_EREPAIR_THRESHOLD_FIELD + 1 + + DMI_EREPAIR_THRESHOLD_FIELD + 1 + + A_EREPAIR_THRESHOLD_MNFG + 0 + + DMI_EREPAIR_THRESHOLD_MNFG + 0 + + X_EREPAIR_THRESHOLD_MNFG + 0 + + MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_MBA + 96 + + MRW_SAFEMODE_MEM_THROTTLE_DENOMINATOR + 512 + + MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP + 32 + + MRW_THERMAL_MEMORY_POWER_LIMIT + 5000 + @@ -330,9 +366,7 @@ PM_SPIVID_PORT_ENABLE 0b100 - PM_SLEEP_TYPE - 1 - + PM_SLEEP_TYPE PM_APSS_CHIP_SELECT 0x00 @@ -722,6 +756,9 @@ 0x0003E08000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -744,6 +781,9 @@ 0x0003E0A000000000 + EI_BUS_TX_MSBSWAP + 1 + @@ -766,6 +806,9 @@ 0x0003E0C000000000 + EI_BUS_TX_MSBSWAP + 1 + @@ -788,6 +831,9 @@ 0x0003E0E000000000 + EI_BUS_TX_MSBSWAP + 1 + @@ -868,6 +914,9 @@ CHIP_UNIT 0 + EI_BUS_TX_MSBSWAP + 0 + @@ -894,6 +943,9 @@ PEER_PATH physical:sys-0/node-0/proc-2/abus-1 + EI_BUS_TX_MSBSWAP + 1 + @@ -920,6 +972,9 @@ PEER_PATH physical:sys-0/node-0/proc-2/abus-2 + EI_BUS_TX_MSBSWAP + 1 + @@ -1066,15 +1121,9 @@ PM_SPIVID_PORT_ENABLE 0b000 - PM_SLEEP_ENTRY - 1 - - PM_SLEEP_EXIT - 1 - - PM_SLEEP_TYPE - 1 - + PM_SLEEP_ENTRY + PM_SLEEP_EXIT + PM_SLEEP_TYPE PM_APSS_CHIP_SELECT 0xFF @@ -1466,6 +1515,9 @@ 0x0003E18000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -1488,6 +1540,9 @@ 0x0003E1A000000000 + EI_BUS_TX_MSBSWAP + 1 + @@ -1510,6 +1565,9 @@ 0x0003E1C000000000 + EI_BUS_TX_MSBSWAP + 1 + @@ -1532,6 +1590,9 @@ 0x0003E1E000000000 + EI_BUS_TX_MSBSWAP + 1 + @@ -1612,6 +1673,9 @@ CHIP_UNIT 0 + EI_BUS_TX_MSBSWAP + 0 + @@ -1638,6 +1702,9 @@ PEER_PATH physical:sys-0/node-0/proc-3/abus-1 + EI_BUS_TX_MSBSWAP + 1 + @@ -1664,6 +1731,9 @@ PEER_PATH physical:sys-0/node-0/proc-3/abus-2 + EI_BUS_TX_MSBSWAP + 1 + @@ -1808,15 +1878,9 @@ PM_PSTATE_UNDERVOLTING_MAXIMUM 1250 - PM_SLEEP_ENTRY - 1 - - PM_SLEEP_EXIT - 1 - - PM_SLEEP_TYPE - 1 - + PM_SLEEP_ENTRY + PM_SLEEP_EXIT + PM_SLEEP_TYPE PM_APSS_CHIP_SELECT 0xFF @@ -2209,6 +2273,9 @@ 0x0003E48000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -2231,6 +2298,9 @@ 0x0003E4A000000000 + EI_BUS_TX_MSBSWAP + 1 + @@ -2253,6 +2323,9 @@ 0x0003E4C000000000 + EI_BUS_TX_MSBSWAP + 1 + @@ -2275,6 +2348,9 @@ 0x0003E4E000000000 + EI_BUS_TX_MSBSWAP + 1 + @@ -2355,6 +2431,9 @@ CHIP_UNIT 0 + EI_BUS_TX_MSBSWAP + 0 + @@ -2381,6 +2460,9 @@ PEER_PATH physical:sys-0/node-0/proc-0/abus-1 + EI_BUS_TX_MSBSWAP + 1 + @@ -2407,6 +2489,9 @@ PEER_PATH physical:sys-0/node-0/proc-0/abus-2 + EI_BUS_TX_MSBSWAP + 1 + @@ -2553,15 +2638,9 @@ PM_SPIVID_PORT_ENABLE 0b000 - PM_SLEEP_ENTRY - 1 - - PM_SLEEP_EXIT - 1 - - PM_SLEEP_TYPE - 1 - + PM_SLEEP_ENTRY + PM_SLEEP_EXIT + PM_SLEEP_TYPE PM_APSS_CHIP_SELECT 0xFF @@ -2952,6 +3031,9 @@ 0x0003E58000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -2974,6 +3056,9 @@ 0x0003E5A000000000 + EI_BUS_TX_MSBSWAP + 1 + @@ -2996,6 +3081,9 @@ 0x0003E5C000000000 + EI_BUS_TX_MSBSWAP + 1 + @@ -3018,6 +3106,9 @@ 0x0003E5E000000000 + EI_BUS_TX_MSBSWAP + 1 + @@ -3098,6 +3189,9 @@ CHIP_UNIT 0 + EI_BUS_TX_MSBSWAP + 0 + @@ -3124,6 +3218,9 @@ PEER_PATH physical:sys-0/node-0/proc-1/abus-1 + EI_BUS_TX_MSBSWAP + 1 + @@ -3150,6 +3247,9 @@ PEER_PATH physical:sys-0/node-0/proc-1/abus-2 + EI_BUS_TX_MSBSWAP + 1 + @@ -3223,6 +3323,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 0 + @@ -3330,6 +3433,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 1 + @@ -3437,6 +3543,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 1 + @@ -3544,6 +3653,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 1 + @@ -3650,6 +3762,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 0 + @@ -3757,6 +3872,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 1 + @@ -3864,6 +3982,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 1 + @@ -3971,6 +4092,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 1 + @@ -4077,6 +4201,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 0 + @@ -4184,6 +4311,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 1 + @@ -4291,6 +4421,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 1 + @@ -4398,6 +4531,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 1 + @@ -4504,6 +4640,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 0 + @@ -4611,6 +4750,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 1 + @@ -4718,6 +4860,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 1 + @@ -4825,6 +4970,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 1 + diff --git a/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml b/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml index 4d9022841..79db7a86f 100644 --- a/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml +++ b/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml @@ -185,6 +185,43 @@ PM_SPIVID_FREQUENCY 10 + MAX_EXS_PER_PROC_CHIP + 12 + + MAX_MCS_PER_SYSTEM + 64 + + X_EREPAIR_THRESHOLD_FIELD + 1 + + A_EREPAIR_THRESHOLD_FIELD + 1 + + DMI_EREPAIR_THRESHOLD_FIELD + 1 + + X_EREPAIR_THRESHOLD_MNFG + 0 + + A_EREPAIR_THRESHOLD_MNFG + 0 + + DMI_EREPAIR_THRESHOLD_MNFG + 0 + + MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_MBA + 96 + + MRW_SAFEMODE_MEM_THROTTLE_DENOMINATOR + 512 + + MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP + 32 + + MRW_THERMAL_MEMORY_POWER_LIMIT + 5000 + + @@ -302,15 +339,9 @@ PM_SPIVID_PORT_ENABLE 0b111 - PM_SLEEP_ENTRY - 1 - - PM_SLEEP_EXIT - 1 - - PM_SLEEP_TYPE - 1 - + PM_SLEEP_ENTRY + PM_SLEEP_EXIT + PM_SLEEP_TYPE PM_APSS_CHIP_SELECT 0x00 @@ -917,6 +948,9 @@ 0x0003E00000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -939,6 +973,9 @@ 0x0003E02000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -961,6 +998,9 @@ 0x0003E04000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -983,6 +1023,9 @@ 0x0003E06000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -1005,6 +1048,9 @@ 0x0003E08000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -1027,6 +1073,9 @@ 0x0003E0A000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -1049,6 +1098,9 @@ 0x0003E0C000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -1071,6 +1123,9 @@ 0x0003E0E000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -1144,6 +1199,9 @@ PEER_PATH physical:sys-0/node-0/proc-6/abus-2 + EI_BUS_TX_MSBSWAP + 0 + @@ -1170,6 +1228,9 @@ PEER_PATH physical:sys-0/node-0/proc-4/abus-1 + EI_BUS_TX_MSBSWAP + 0 + @@ -1196,6 +1257,9 @@ PEER_PATH physical:sys-0/node-0/proc-2/abus-0 + EI_BUS_TX_MSBSWAP + 0 + @@ -1396,15 +1460,9 @@ PM_SPIVID_PORT_ENABLE 0b111 - PM_SLEEP_ENTRY - 1 - - PM_SLEEP_EXIT - 1 - - PM_SLEEP_TYPE - 1 - + PM_SLEEP_ENTRY + PM_SLEEP_EXIT + PM_SLEEP_TYPE PM_APSS_CHIP_SELECT 0x00 @@ -2011,6 +2069,9 @@ 0x0003E10000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -2033,6 +2094,9 @@ 0x0003E12000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -2055,6 +2119,9 @@ 0x0003E14000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -2077,6 +2144,9 @@ 0x0003E16000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -2099,6 +2169,9 @@ 0x0003E18000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -2121,6 +2194,9 @@ 0x0003E1A000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -2143,6 +2219,9 @@ 0x0003E1C000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -2165,6 +2244,9 @@ 0x0003E1E000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -2237,6 +2319,9 @@ PEER_PATH physical:sys-0/node-0/proc-7/abus-2 + EI_BUS_TX_MSBSWAP + 0 + @@ -2263,6 +2348,9 @@ PEER_PATH physical:sys-0/node-0/proc-5/abus-1 + EI_BUS_TX_MSBSWAP + 0 + @@ -2289,6 +2377,9 @@ PEER_PATH physical:sys-0/node-0/proc-3/abus-0 + EI_BUS_TX_MSBSWAP + 0 + @@ -2490,15 +2581,9 @@ PM_SPIVID_PORT_ENABLE 0b111 - PM_SLEEP_ENTRY - 1 - - PM_SLEEP_EXIT - 1 - - PM_SLEEP_TYPE - 1 - + PM_SLEEP_ENTRY + PM_SLEEP_EXIT + PM_SLEEP_TYPE PM_APSS_CHIP_SELECT 0x00 @@ -3104,6 +3189,9 @@ 0x0003E20000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -3126,6 +3214,9 @@ 0x0003E22000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -3148,6 +3239,9 @@ 0x0003E24000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -3170,6 +3264,9 @@ 0x0003E26000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -3192,6 +3289,9 @@ 0x0003E28000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -3214,6 +3314,9 @@ 0x0003E2A000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -3236,6 +3339,9 @@ 0x0003E2C000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -3258,6 +3364,9 @@ 0x0003E2E000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -3330,6 +3439,9 @@ PEER_PATH physical:sys-0/node-0/proc-0/abus-2 + EI_BUS_TX_MSBSWAP + 0 + @@ -3356,6 +3468,9 @@ PEER_PATH physical:sys-0/node-0/proc-6/abus-1 + EI_BUS_TX_MSBSWAP + 0 + @@ -3382,6 +3497,9 @@ PEER_PATH physical:sys-0/node-0/proc-4/abus-0 + EI_BUS_TX_MSBSWAP + 0 + @@ -3583,15 +3701,9 @@ PM_SPIVID_PORT_ENABLE 0b111 - PM_SLEEP_ENTRY - 1 - - PM_SLEEP_EXIT - 1 - - PM_SLEEP_TYPE - 1 - + PM_SLEEP_ENTRY + PM_SLEEP_EXIT + PM_SLEEP_TYPE PM_APSS_CHIP_SELECT 0x00 @@ -4198,6 +4310,9 @@ 0x0003E30000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -4220,6 +4335,9 @@ 0x0003E32000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -4242,6 +4360,9 @@ 0x0003E34000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -4264,6 +4385,9 @@ 0x0003E36000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -4286,6 +4410,9 @@ 0x0003E38000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -4308,6 +4435,9 @@ 0x0003E3A000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -4330,6 +4460,9 @@ 0x0003E3C000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -4352,6 +4485,9 @@ 0x0003E3E000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -4424,6 +4560,9 @@ PEER_PATH physical:sys-0/node-0/proc-1/abus-2 + EI_BUS_TX_MSBSWAP + 0 + @@ -4450,6 +4589,9 @@ PEER_PATH physical:sys-0/node-0/proc-7/abus-1 + EI_BUS_TX_MSBSWAP + 0 + @@ -4476,6 +4618,9 @@ PEER_PATH physical:sys-0/node-0/proc-5/abus-0 + EI_BUS_TX_MSBSWAP + 0 + @@ -4675,15 +4820,9 @@ PM_SPIVID_PORT_ENABLE 0b111 - PM_SLEEP_ENTRY - 1 - - PM_SLEEP_EXIT - 1 - - PM_SLEEP_TYPE - 1 - + PM_SLEEP_ENTRY + PM_SLEEP_EXIT + PM_SLEEP_TYPE PM_APSS_CHIP_SELECT 0x00 @@ -5769,15 +5908,9 @@ PM_SPIVID_PORT_ENABLE 0b111 - PM_SLEEP_ENTRY - 1 - - PM_SLEEP_EXIT - 1 - - PM_SLEEP_TYPE - 1 - + PM_SLEEP_ENTRY + PM_SLEEP_EXIT + PM_SLEEP_TYPE PM_APSS_CHIP_SELECT 0x00 @@ -6861,15 +6994,9 @@ PM_SPIVID_PORT_ENABLE 0b111 - PM_SLEEP_ENTRY - 1 - - PM_SLEEP_EXIT - 1 - - PM_SLEEP_TYPE - 1 - + PM_SLEEP_ENTRY + PM_SLEEP_EXIT + PM_SLEEP_TYPE PM_APSS_CHIP_SELECT 0x00 @@ -7954,15 +8081,9 @@ PM_SPIVID_PORT_ENABLE 0b111 - PM_SLEEP_ENTRY - 1 - - PM_SLEEP_EXIT - 1 - - PM_SLEEP_TYPE - 1 - + PM_SLEEP_ENTRY + PM_SLEEP_EXIT + PM_SLEEP_TYPE PM_APSS_CHIP_SELECT 0x00 @@ -8973,6 +9094,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 0 + @@ -9080,6 +9204,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 0 + @@ -9187,6 +9314,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 0 + @@ -9294,6 +9424,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 0 + @@ -9401,6 +9534,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 0 + @@ -9508,6 +9644,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 0 + @@ -9615,6 +9754,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 0 + @@ -9722,6 +9864,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 0 + @@ -9829,6 +9974,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 0 + @@ -9936,6 +10084,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 0 + @@ -10043,6 +10194,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 0 + @@ -10150,6 +10304,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 0 + @@ -10257,6 +10414,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 0 + @@ -10364,6 +10524,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 0 + @@ -10471,6 +10634,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 0 + @@ -10578,6 +10744,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 0 + @@ -10685,6 +10854,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 0 + @@ -10792,6 +10964,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 0 + @@ -10899,6 +11074,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 0 + @@ -11006,6 +11184,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 0 + @@ -11113,6 +11294,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 0 + @@ -11220,6 +11404,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 0 + @@ -11327,6 +11514,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 0 + @@ -11434,6 +11624,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 0 + @@ -11541,6 +11734,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 0 + @@ -11648,6 +11844,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 0 + @@ -11755,6 +11954,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 0 + @@ -11862,6 +12064,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 0 + @@ -11969,6 +12174,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 0 + @@ -12076,6 +12284,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 0 + @@ -12183,6 +12394,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 0 + @@ -12290,6 +12504,9 @@ engine0 + EI_BUS_TX_MSBSWAP + 0 + @@ -15878,15 +16095,9 @@ PM_SPIVID_PORT_ENABLE 0b111 - PM_SLEEP_ENTRY - 1 - - PM_SLEEP_EXIT - 1 - - PM_SLEEP_TYPE - 1 - + PM_SLEEP_ENTRY + PM_SLEEP_EXIT + PM_SLEEP_TYPE PM_APSS_CHIP_SELECT 0x00 diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml index f1dd2083b..c0ddc3751 100644 --- a/src/usr/targeting/common/xmltohb/target_types.xml +++ b/src/usr/targeting/common/xmltohb/target_types.xml @@ -169,10 +169,22 @@ MAX_PROC_CHIPS_PER_NODE MAX_EXS_PER_PROC_CHIP - MAX_DIMMS_PER_MBA_PORT - MAX_MBA_PORTS_PER_MBA - MAX_MBAS_PER_MEMBUF_CHIP - MAX_CHIPLETS_PER_PROC + + MAX_DIMMS_PER_MBA_PORT + 2 + + + MAX_MBA_PORTS_PER_MBA + 2 + + + MAX_MBAS_PER_MEMBUF_CHIP + 2 + + + MAX_CHIPLETS_PER_PROC + 32 + MAX_MCS_PER_SYSTEM PROC_PBIEX_ASYNC_SEL @@ -208,6 +220,7 @@ FSI_MASTER_TYPE + NO_MASTER FSI_MASTER_PORT @@ -1176,7 +1189,6 @@ MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA MEMB_TP_BNDY_PLL_NEST4800_MEM1866_LENGTH MSS_FREQ_BIAS_PERCENTAGE - MEMB_NEST_FREQ CDIMM_SENSOR_MAP_PRIMARY CDIMM_SENSOR_MAP_SECONDARY MSS_BLUEWATERFALL_BROKEN diff --git a/src/usr/targeting/common/xmltohb/vbu_MURANO.system.xml b/src/usr/targeting/common/xmltohb/vbu_MURANO.system.xml index 3ff3edeba..d094c0fe6 100644 --- a/src/usr/targeting/common/xmltohb/vbu_MURANO.system.xml +++ b/src/usr/targeting/common/xmltohb/vbu_MURANO.system.xml @@ -158,6 +158,86 @@ MSS_CLEANER_ENABLE 1 + + PROC_R_LOADLINE + 890 + + PROC_R_DISTLOSS + 100 + + PROC_VRM_VOFFSET + 1000 + + FREQ_CORE_MAX + 4000 + + PM_EXTERNAL_VRM_STEPSIZE + 2500 + + PM_EXTERNAL_VRM_STEPDELAY + 10 + + PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY + 2000 + + PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY + 2300 + + PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY + 3000 + + PM_RESONANT_CLOCK_HIGH_BAND_LOWER_FREQUENCY + 3050 + + PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY + 4800 + + PM_SAFE_FREQUENCY + 3200 + + PM_SPIPSS_FREQUENCY + 10 + + PM_SPIVID_FREQUENCY + 0b11 + + + MAX_EXS_PER_PROC_CHIP + 6 + + MAX_MCS_PER_SYSTEM + 4 + + X_EREPAIR_THRESHOLD_FIELD + 1 + + A_EREPAIR_THRESHOLD_FIELD + 1 + + DMI_EREPAIR_THRESHOLD_FIELD + 1 + + A_EREPAIR_THRESHOLD_MNFG + 0 + + DMI_EREPAIR_THRESHOLD_MNFG + 0 + + X_EREPAIR_THRESHOLD_MNFG + 0 + + MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_MBA + 96 + + MRW_SAFEMODE_MEM_THROTTLE_DENOMINATOR + 512 + + MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP + 32 + + MRW_THERMAL_MEMORY_POWER_LIMIT + 5000 + @@ -459,6 +539,9 @@ 0x0003E08000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -481,6 +564,9 @@ 0x0003E0A000000000 + EI_BUS_TX_MSBSWAP + 1 + @@ -503,6 +589,9 @@ 0x0003E0C000000000 + EI_BUS_TX_MSBSWAP + 1 + @@ -525,6 +614,9 @@ 0x0003E0E000000000 + EI_BUS_TX_MSBSWAP + 1 + @@ -606,6 +698,9 @@ CHIP_UNIT 0 + EI_BUS_TX_MSBSWAP + 0 + @@ -632,6 +727,9 @@ PEER_PATH physical:sys-0/node-0/proc-2/abus-0 + EI_BUS_TX_MSBSWAP + 1 + @@ -654,6 +752,9 @@ CHIP_UNIT 2 + EI_BUS_TX_MSBSWAP + 1 + @@ -888,6 +989,9 @@ CHIP_UNIT 4 + EI_BUS_TX_MSBSWAP + 0 + @@ -906,6 +1010,9 @@ CHIP_UNIT 5 + EI_BUS_TX_MSBSWAP + 1 + @@ -924,6 +1031,9 @@ CHIP_UNIT 6 + EI_BUS_TX_MSBSWAP + 1 + @@ -942,6 +1052,9 @@ CHIP_UNIT 7 + EI_BUS_TX_MSBSWAP + 1 + @@ -1022,6 +1135,9 @@ CHIP_UNIT 0 + EI_BUS_TX_MSBSWAP + 0 + @@ -1048,6 +1164,9 @@ PEER_PATH physical:sys-0/node-0/proc-3/abus-0 + EI_BUS_TX_MSBSWAP + 1 + @@ -1070,6 +1189,9 @@ CHIP_UNIT 2 + EI_BUS_TX_MSBSWAP + 1 + @@ -1303,6 +1425,9 @@ CHIP_UNIT 4 + EI_BUS_TX_MSBSWAP + 0 + @@ -1321,6 +1446,9 @@ CHIP_UNIT 5 + EI_BUS_TX_MSBSWAP + 1 + @@ -1339,6 +1467,9 @@ CHIP_UNIT 6 + EI_BUS_TX_MSBSWAP + 1 + @@ -1357,6 +1488,9 @@ CHIP_UNIT 7 + EI_BUS_TX_MSBSWAP + 1 + @@ -1441,6 +1575,9 @@ PEER_PATH physical:sys-0/node-0/proc-0/abus-1 + EI_BUS_TX_MSBSWAP + 0 + @@ -1463,6 +1600,9 @@ CHIP_UNIT 1 + EI_BUS_TX_MSBSWAP + 1 + @@ -1485,6 +1625,9 @@ CHIP_UNIT 2 + EI_BUS_TX_MSBSWAP + 1 + @@ -1718,6 +1861,9 @@ CHIP_UNIT 4 + EI_BUS_TX_MSBSWAP + 0 + @@ -1736,6 +1882,9 @@ CHIP_UNIT 5 + EI_BUS_TX_MSBSWAP + 1 + @@ -1754,6 +1903,9 @@ CHIP_UNIT 6 + EI_BUS_TX_MSBSWAP + 1 + @@ -1772,6 +1924,9 @@ CHIP_UNIT 7 + EI_BUS_TX_MSBSWAP + 1 + @@ -1856,6 +2011,9 @@ PEER_PATH physical:sys-0/node-0/proc-1/abus-1 + EI_BUS_TX_MSBSWAP + 0 + @@ -1878,6 +2036,9 @@ CHIP_UNIT 1 + EI_BUS_TX_MSBSWAP + 1 + @@ -1900,6 +2061,9 @@ CHIP_UNIT 2 + EI_BUS_TX_MSBSWAP + 1 + @@ -1965,6 +2129,9 @@ 0 VPD_REC_NUM4 + EI_BUS_TX_MSBSWAP + 0 + @@ -2061,6 +2228,9 @@ 0 VPD_REC_NUM5 + EI_BUS_TX_MSBSWAP + 1 + @@ -2158,6 +2328,9 @@ 0 VPD_REC_NUM20 + EI_BUS_TX_MSBSWAP + 0 + @@ -2256,6 +2429,9 @@ 0 VPD_REC_NUM21 + EI_BUS_TX_MSBSWAP + 1 + diff --git a/src/usr/targeting/common/xmltohb/vbu_VENICE.system.xml b/src/usr/targeting/common/xmltohb/vbu_VENICE.system.xml index 7b2fb0040..5206f5a88 100644 --- a/src/usr/targeting/common/xmltohb/vbu_VENICE.system.xml +++ b/src/usr/targeting/common/xmltohb/vbu_VENICE.system.xml @@ -203,6 +203,42 @@ IS_SIMULATION 1 + MAX_EXS_PER_PROC_CHIP + 12 + + MAX_MCS_PER_SYSTEM + 8 + + X_EREPAIR_THRESHOLD_FIELD + 1 + + A_EREPAIR_THRESHOLD_FIELD + 1 + + DMI_EREPAIR_THRESHOLD_FIELD + 1 + + X_EREPAIR_THRESHOLD_MNFG + 0 + + A_EREPAIR_THRESHOLD_MNFG + 0 + + DMI_EREPAIR_THRESHOLD_MNFG + 0 + + MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_MBA + 96 + + MRW_SAFEMODE_MEM_THROTTLE_DENOMINATOR + 512 + + MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP + 32 + + MRW_THERMAL_MEMORY_POWER_LIMIT + 5000 + @@ -960,6 +996,9 @@ 0x0003E00000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -982,6 +1021,9 @@ 0x0003E02000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -1004,6 +1046,9 @@ 0x0003E04000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -1026,6 +1071,9 @@ 0x0003E06000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -1193,6 +1253,9 @@ CHIP_UNIT 0 + EI_BUS_TX_MSBSWAP + 0 + @@ -1214,7 +1277,10 @@ CHIP_UNIT 1 - + + EI_BUS_TX_MSBSWAP + 0 + @@ -1237,6 +1303,9 @@ CHIP_UNIT 2 + EI_BUS_TX_MSBSWAP + 0 + @@ -2065,6 +2134,9 @@ 0x0003E10000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -2087,6 +2159,9 @@ 0x0003E12000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -2109,6 +2184,9 @@ 0x0003E14000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -2131,6 +2209,9 @@ 0x0003E16000000000 + EI_BUS_TX_MSBSWAP + 0 + @@ -2285,6 +2379,9 @@ CHIP_UNIT 0 + EI_BUS_TX_MSBSWAP + 0 + @@ -2307,6 +2404,9 @@ CHIP_UNIT 1 + EI_BUS_TX_MSBSWAP + 0 + @@ -2329,6 +2429,9 @@ CHIP_UNIT 2 + EI_BUS_TX_MSBSWAP + 0 + @@ -2449,6 +2552,9 @@ VPD_REC_NUM0 MSS_CACHE_ENABLE1 + EI_BUS_TX_MSBSWAP + 0 + @@ -2548,6 +2654,9 @@ VPD_REC_NUM1 MSS_CACHE_ENABLE1 + EI_BUS_TX_MSBSWAP + 0 + @@ -2646,6 +2755,9 @@ 0 VPD_REC_NUM2 + EI_BUS_TX_MSBSWAP + 0 + @@ -2744,6 +2856,9 @@ 0 VPD_REC_NUM3 + EI_BUS_TX_MSBSWAP + 0 + @@ -2842,6 +2957,9 @@ 0 VPD_REC_NUM4 + EI_BUS_TX_MSBSWAP + 0 + @@ -2940,6 +3058,9 @@ 0 VPD_REC_NUM5 + EI_BUS_TX_MSBSWAP + 0 + @@ -3038,6 +3159,9 @@ 0 VPD_REC_NUM6 + EI_BUS_TX_MSBSWAP + 0 + @@ -3136,6 +3260,9 @@ 0 VPD_REC_NUM7 + EI_BUS_TX_MSBSWAP + 0 + -- cgit v1.2.1