From 5962066104e3a4aa84440f73af50efc67f674fc2 Mon Sep 17 00:00:00 2001 From: Nico Fajardo Date: Thu, 9 Jan 2020 08:56:28 -0600 Subject: Unmask after draminit and draminit_mc; cmd complete - Define after_* functions and unmasking operations - Add FAPI_TRY calls to after_* functions in exp_draminit files - Add SRQFIR, MCBISTFIR, and RDFFIR register traits to exp_fir_traits.H - after_draminit and after_draminit_mc unit tests Change-Id: Ie7e6fcfd4b71259e88ad1f804b3da015c9faabf1 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/89488 Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Tested-by: Hostboot CI Reviewed-by: NICOLAS R FAJARDO Reviewed-by: Louis Stermole Reviewed-by: Mark Pizzutillo Reviewed-by: Marc Gollub Reviewed-by: Caleb N Palmer Reviewed-by: Jennifer A Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/89525 Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Daniel M Crowell --- .../explorer/procedures/hwp/memory/exp_draminit.C | 6 +- .../procedures/hwp/memory/exp_draminit_mc.C | 8 +- .../procedures/hwp/memory/lib/fir/exp_fir.H | 4 +- .../procedures/hwp/memory/lib/fir/exp_fir_traits.H | 75 ++++++++++++++++++ .../procedures/hwp/memory/lib/fir/exp_unmask.C | 92 ++++++++++++++++++++-- 5 files changed, 172 insertions(+), 13 deletions(-) diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit.C index 67ddf14d5..bc9187fbe 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018,2019 */ +/* Contributors Listed Below - COPYRIGHT 2018,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -42,6 +42,7 @@ #include #include #include +#include extern "C" { @@ -86,6 +87,9 @@ extern "C" FAPI_TRY(mss::exp::host_fw_phy_init_with_eye_capture(i_target, l_crc, l_phy_params)); } + // Unmask registers after draminit training + FAPI_TRY(mss::unmask::after_draminit_training(i_target), "%s Failed after_draminit_training", mss::c_str(i_target)); + return fapi2::FAPI2_RC_SUCCESS; fapi_try_exit: diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit_mc.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit_mc.C index b2647eb34..bbc86d830 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit_mc.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit_mc.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018,2019 */ +/* Contributors Listed Below - COPYRIGHT 2018,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -41,6 +41,7 @@ #include #include +#include extern "C" { @@ -97,9 +98,8 @@ extern "C" // Apply marks from OCMB VPD FAPI_TRY( mss::apply_mark_store(i_target), "%s Failed enable_read_ecc", mss::c_str(i_target) ); - // TODO: Move mss::unmask::after_draminit_mc to generic and call it - // At this point the DDR interface must be monitored for memory errors. Memory related FIRs should be unmasked. - //FAPI_TRY( mss::unmask::after_draminit_mc(i_target), "%s Failed after_draminit_mc", mss::c_str(i_target) ); + // Unmask registers after draminit_mc + FAPI_TRY(mss::unmask::after_draminit_mc(i_target), "%s Failed after_draminit_mc", mss::c_str(i_target)); fapi_try_exit: FAPI_INF("%s End exp_draminit MC", mss::c_str(i_target)); diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/fir/exp_fir.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/fir/exp_fir.H index 905013b66..84937976a 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/fir/exp_fir.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/fir/exp_fir.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2019 */ +/* Contributors Listed Below - COPYRIGHT 2019,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -44,5 +44,5 @@ namespace mss // FIR Register Traits for Explorer will be here sooner or later. -} +} // end mss ns #endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/fir/exp_fir_traits.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/fir/exp_fir_traits.H index 06d03488b..3fb3460dc 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/fir/exp_fir_traits.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/fir/exp_fir_traits.H @@ -22,3 +22,78 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ +/// +/// @file exp_fir_traits.H +/// @brief Memory subsystem FIR support +/// +// *HWP HWP Owner: Stephen Glancy +// *HWP HWP Backup: Andre Marin +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: FSP:HB + +#ifndef _MSS_EXP_FIR_TRAITS_H_ +#define _MSS_EXP_FIR_TRAITS_H_ + +#include +#include +#include +#include +#include + +namespace mss +{ + +/// +/// @brief FIR Register Traits for Explorer MCBIST FIR +/// +template <> +struct firTraits +{ + static constexpr uint64_t REG = EXPLR_MCBIST_MCBISTFIRQ; + static constexpr uint64_t ACT0 = EXPLR_MCBIST_MCBISTFIRACT0; + static constexpr uint64_t ACT1 = EXPLR_MCBIST_MCBISTFIRACT1; + static constexpr uint64_t MASK = EXPLR_MCBIST_MCBISTFIRMASK; + static constexpr uint64_t MASK_AND = EXPLR_MCBIST_MCBISTFIRMASK_AND; + static constexpr uint64_t MASK_OR = EXPLR_MCBIST_MCBISTFIRMASK_OR; + + // Target type of this register + static constexpr fapi2::TargetType T = fapi2::TARGET_TYPE_OCMB_CHIP; +}; + +/// +/// @brief FIR Register Traits for Explorer SRQ FIR +/// +template <> +struct firTraits +{ + static constexpr uint64_t REG = EXPLR_SRQ_SRQFIRQ; + static constexpr uint64_t ACT0 = EXPLR_SRQ_SRQFIR_ACTION0; + static constexpr uint64_t ACT1 = EXPLR_SRQ_SRQFIR_ACTION1; + static constexpr uint64_t MASK = EXPLR_SRQ_SRQFIR_MASK; + static constexpr uint64_t MASK_AND = EXPLR_SRQ_SRQFIR_MASK_AND; + static constexpr uint64_t MASK_OR = EXPLR_SRQ_SRQFIR_MASK_OR; + + // Target type of this register + static constexpr fapi2::TargetType T = fapi2::TARGET_TYPE_OCMB_CHIP; +}; + +/// +/// @brief FIR Register Traits for Explorer RDF FIR +/// +template <> +struct firTraits +{ + static constexpr uint64_t REG = EXPLR_RDF_FIR; + static constexpr uint64_t ACT0 = EXPLR_RDF_ACTION0; + static constexpr uint64_t ACT1 = EXPLR_RDF_ACTION1; + static constexpr uint64_t MASK = EXPLR_RDF_MASK; + static constexpr uint64_t MASK_AND = EXPLR_RDF_MASK_AND; + static constexpr uint64_t MASK_OR = EXPLR_RDF_MASK_OR; + + // Target type of this register + static constexpr fapi2::TargetType T = fapi2::TARGET_TYPE_OCMB_CHIP; +}; + +} // end mss ns +#endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/fir/exp_unmask.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/fir/exp_unmask.C index 2d35dd256..49137f3e2 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/fir/exp_unmask.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/fir/exp_unmask.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2019 */ +/* Contributors Listed Below - COPYRIGHT 2019,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -23,7 +23,7 @@ /* */ /* IBM_PROLOG_END_TAG */ /// -/// @file unmask.C +/// @file exp_unmask.C /// @brief Subroutines for unmasking and setting up MSS FIR /// // *HWP HWP Owner: Stephen Glancy @@ -38,6 +38,7 @@ #include #include #include +#include #include namespace mss @@ -50,24 +51,103 @@ namespace unmask /// @brief Unmask and setup actions performed after draminit_mc /// @param[in] i_target the fapi2::Target /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok -/// TODO: Need to implement this function +/// template<> fapi2::ReturnCode after_draminit_mc( const fapi2::Target& i_target ) { + fapi2::ReturnCode l_rc1 = fapi2::FAPI2_RC_SUCCESS; + fapi2::ReturnCode l_rc2 = fapi2::FAPI2_RC_SUCCESS; + fapi2::ReturnCode l_rc3 = fapi2::FAPI2_RC_SUCCESS; + + // Create registers and check success for MCBISTFIR and SRQFIR and RDFFIR + mss::fir::reg l_exp_mcbist_reg(i_target, l_rc1); + mss::fir::reg l_exp_srq_reg(i_target, l_rc2); + mss::fir::reg l_exp_rdf_reg(i_target, l_rc3); + + FAPI_TRY(l_rc1, "unable to create fir::reg for %d", EXPLR_MCBIST_MCBISTFIRQ); + FAPI_TRY(l_rc2, "unable to create fir::reg for %d", EXPLR_SRQ_SRQFIRQ); + FAPI_TRY(l_rc3, "unable to create fir::reg for %d", EXPLR_RDF_FIR); + + // Write MCBISTFIR register per Explorer unmask spec + FAPI_TRY(l_exp_mcbist_reg.attention() + .write()); + + // Write RDF FIR register per Explorer unmask spec + // TK Need to set EXPLR_RDF_FIR_MAINTENANCE_RCD to recoverable for planar/ISDIMM + FAPI_TRY(l_exp_rdf_reg.recoverable_error() + .recoverable_error() + .recoverable_error() + .recoverable_error() + .recoverable_error() + .checkstop() + .checkstop() + .recoverable_error() + .recoverable_error() + .checkstop() + .checkstop() + .write()); + + // Write SRQ FIR register per Explorer unmask spec + FAPI_TRY(l_exp_srq_reg.recoverable_error() + .write()); + return fapi2::FAPI2_RC_SUCCESS; + +fapi_try_exit: + + FAPI_DBG("Exiting with return code : 0x%08X...", (uint64_t) fapi2::current_err); + return fapi2::current_err; } /// /// @brief Unmask and setup actions performed after draminit_training /// @param[in] i_target the fapi2::Target /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok -/// TODO: Need to implement this function +/// template<> fapi2::ReturnCode after_draminit_training( const fapi2::Target& i_target ) { + fapi2::ReturnCode l_rc1 = fapi2::FAPI2_RC_SUCCESS; + fapi2::ReturnCode l_rc2 = fapi2::FAPI2_RC_SUCCESS; + + // Create registers and check success for MCBISTFIR and SRQFIR + mss::fir::reg l_exp_mcbist_reg(i_target, l_rc1); + mss::fir::reg l_exp_srq_reg(i_target, l_rc2); + + FAPI_TRY(l_rc1, "unable to create fir::reg for %d", EXPLR_MCBIST_MCBISTFIRQ); + FAPI_TRY(l_rc2, "unable to create fir::reg for %d", EXPLR_SRQ_SRQFIRQ); + + // Write MCBISTFIR register per Explorer unmask spec; omit bit 10 cmd_complete until draminit_mc + FAPI_TRY(l_exp_mcbist_reg.recoverable_error() + .checkstop() + .checkstop() + .recoverable_error() + .checkstop() + .write()); + + // Write SRQ FIR register per Explorer unmask spec + FAPI_TRY(l_exp_srq_reg.recoverable_error() + .checkstop() + .recoverable_error() + .checkstop() + .checkstop() + .checkstop() + .checkstop() + .recoverable_error() + .checkstop() + .checkstop() + .checkstop() + .recoverable_error() + .write()); + return fapi2::FAPI2_RC_SUCCESS; + +fapi_try_exit: + + FAPI_DBG("Exiting with return code : 0x%08X...", (uint64_t) fapi2::current_err); + return fapi2::current_err; } /// @@ -115,5 +195,5 @@ fapi2::ReturnCode after_background_scrub( const fapi2::T return fapi2::FAPI2_RC_SUCCESS; } -} -} +} // end unmask ns +} // end mss ns -- cgit v1.2.1