From 47c6c834b46b0e9985ce3dead1fe4f83aaafc8c4 Mon Sep 17 00:00:00 2001 From: "Sunil.Kumar" Date: Thu, 11 Feb 2016 09:51:41 -0600 Subject: Level 2 HWP p9_mem_startclocks Change-Id: I27d7e3b1f1797f3b7372f7da07dc48e9c415b4b3 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/24215 Tested-by: Jenkins Server Reviewed-by: Brian Silver Reviewed-by: Soma Bhanutej Reviewed-by: SRINIVAS V. POLISETTY Reviewed-by: Parvathi Rachakonda Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/24610 Reviewed-by: Daniel M. Crowell --- .../p9/procedures/hwp/perv/p9_mem_startclocks.C | 187 ++++++++++++++++++++- .../p9/procedures/hwp/perv/p9_mem_startclocks.H | 25 ++- .../p9/procedures/hwp/perv/p9_mem_startclocks.mk | 3 +- 3 files changed, 200 insertions(+), 15 deletions(-) diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_mem_startclocks.C b/src/import/chips/p9/procedures/hwp/perv/p9_mem_startclocks.C index 264d7013b..ae373c84b 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_mem_startclocks.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_mem_startclocks.C @@ -7,7 +7,7 @@ /* */ /* EKB Project */ /* */ -/* COPYRIGHT 2015 */ +/* COPYRIGHT 2015,2016 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -21,26 +21,201 @@ /// /// @brief Start clocks on MBA/MCAs //------------------------------------------------------------------------------ -// *HWP HW Owner : Anusha Reddy Rangareddygari +// *HWP HW Owner : Abhishek Agarwal // *HWP HW Backup Owner : Srinivas V Naga -// *HWP FW Owner : Sunil Kumar +// *HWP FW Owner : Sunil kumar // *HWP Team : Perv -// *HWP Level : 1 +// *HWP Level : 2 // *HWP Consumed by : HB //------------------------------------------------------------------------------ //## auto_generated #include "p9_mem_startclocks.H" +#include "p9_const_common.H" +#include "p9_misc_scom_addresses_fld.H" +#include "p9_perv_scom_addresses.H" +#include "p9_perv_scom_addresses_fld.H" +#include "p9_quad_scom_addresses_fld.H" +#include "p9_sbe_common.H" +enum P9_MEM_STARTCLOCKS_Private_Constants +{ + CLOCK_CMD = 0x1, + STARTSLAVE = 0x1, + STARTMASTER = 0x1, + REGIONS_ALL_EXCEPT_VITAL_NESTPLL = 0x7FE, + CLOCK_TYPES = 0x7, + DONT_STARTMASTER = 0x0, + DONT_STARTSLAVE = 0x0 +}; + +static fapi2::ReturnCode p9_mem_startclocks_check_checkstop_function( + const fapi2::Target& i_target_chiplet); + +static fapi2::ReturnCode p9_mem_startclocks_cplt_ctrl_action_function( + const fapi2::Target& i_target_chiplet); + +static fapi2::ReturnCode p9_mem_startclocks_flushmode( + const fapi2::Target& i_target_chiplet); + +fapi2::ReturnCode p9_mem_startclocks(const + fapi2::Target& i_target_chip) +{ + FAPI_DBG("Entering ..."); + + FAPI_INF("Switch MC meshs to Nest mesh"); + + for (auto l_trgt_chplt : i_target_chip.getChildren + (fapi2::TARGET_FILTER_ALL_MC, fapi2::TARGET_STATE_FUNCTIONAL)) + { + + FAPI_INF("Call p9_mem_startclocks_cplt_ctrl_action_function for Mc chiplets"); + FAPI_TRY(p9_mem_startclocks_cplt_ctrl_action_function(l_trgt_chplt)); + + FAPI_INF("Call module align chiplets for Mc chiplets"); + FAPI_TRY(p9_sbe_common_align_chiplets(l_trgt_chplt)); + + FAPI_INF("Call module clock start stop for MC01, MC23."); + FAPI_TRY(p9_sbe_common_clock_start_stop(l_trgt_chplt, CLOCK_CMD, + DONT_STARTSLAVE, DONT_STARTMASTER, REGIONS_ALL_EXCEPT_VITAL_NESTPLL, + CLOCK_TYPES)); + + FAPI_INF("Call p9_mem_startclocks_check_checkstop_function for Mc chiplets "); + FAPI_TRY(p9_mem_startclocks_check_checkstop_function(l_trgt_chplt)); + + FAPI_INF("Call p9_mem_startclocks_flushmode for Mc chiplets"); + FAPI_TRY(p9_mem_startclocks_flushmode(l_trgt_chplt)); + + } + + FAPI_DBG("Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief --drop chiplet fence +/// --check checkstop register +/// --clear flush inhibit to go into flush mode +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_mem_startclocks_check_checkstop_function( + const fapi2::Target& i_target_chiplet) +{ + fapi2::buffer l_read_reg; + fapi2::buffer l_data64; + FAPI_DBG("Entering ..."); -fapi2::ReturnCode p9_mem_startclocks(const fapi2::Target& i_target_chiplet) + FAPI_INF("Drop chiplet fence"); + //Setting NET_CTRL0 register value + l_data64.flush<1>(); + l_data64.clearBit(); //NET_CTRL0.FENCE_EN = 0 + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64)); + + FAPI_INF("Check checkstop register"); + //Getting XFIR register value + FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_XFIR, + l_read_reg)); //l_read_reg = XFIR + + FAPI_ASSERT(l_read_reg == 0, + fapi2::READ_ALL_CHECKSTOP_ERR() + .set_READ_ALL_CHECKSTOP(l_read_reg), + "ERROR: COMBINE ALL CHECKSTOP ERROR"); + + FAPI_DBG("Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief --drop vital fence +/// --reset abstclk muxsel and syncclk muxsel +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_mem_startclocks_cplt_ctrl_action_function( + const fapi2::Target& i_target_chiplet) +{ + fapi2::buffer l_data64; + FAPI_DBG("Entering ..."); + + // Local variable and constant definition + fapi2::buffer l_attr_pg; + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PG, i_target_chiplet, l_attr_pg)); + + l_attr_pg.invert(); + + FAPI_INF("Drop partial good fences"); + //Setting CPLT_CTRL1 register value + l_data64.flush<0>(); + //CPLT_CTRL1.TC_VITL_REGION_FENCE = l_attr_pg.getBit<19>() + l_data64.writeBit(l_attr_pg.getBit<19>()); + //CPLT_CTRL1.TC_PERV_REGION_FENCE = l_attr_pg.getBit<20>() + l_data64.writeBit(l_attr_pg.getBit<20>()); + //CPLT_CTRL1.TC_REGION1_FENCE = l_attr_pg.getBit<21>() + l_data64.writeBit(l_attr_pg.getBit<21>()); + //CPLT_CTRL1.TC_REGION2_FENCE = l_attr_pg.getBit<22>() + l_data64.writeBit(l_attr_pg.getBit<22>()); + //CPLT_CTRL1.TC_REGION3_FENCE = l_attr_pg.getBit<23>() + l_data64.writeBit(l_attr_pg.getBit<23>()); + //CPLT_CTRL1.TC_REGION4_FENCE = l_attr_pg.getBit<24>() + l_data64.writeBit(l_attr_pg.getBit<24>()); + //CPLT_CTRL1.TC_REGION5_FENCE = l_attr_pg.getBit<25>() + l_data64.writeBit(l_attr_pg.getBit<25>()); + //CPLT_CTRL1.TC_REGION6_FENCE = l_attr_pg.getBit<26>() + l_data64.writeBit(l_attr_pg.getBit<26>()); + //CPLT_CTRL1.TC_REGION7_FENCE = l_attr_pg.getBit<27>() + l_data64.writeBit(l_attr_pg.getBit<27>()); + //CPLT_CTRL1.UNUSED_12B = l_attr_pg.getBit<28>() + l_data64.writeBit(l_attr_pg.getBit<28>()); + //CPLT_CTRL1.UNUSED_13B = l_attr_pg.getBit<29>() + l_data64.writeBit(l_attr_pg.getBit<29>()); + //CPLT_CTRL1.UNUSED_14B = l_attr_pg.getBit<30>() + l_data64.writeBit(l_attr_pg.getBit<30>()); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_CPLT_CTRL1_CLEAR, l_data64)); + + FAPI_INF("reset abistclk_muxsel and syncclk_muxsel"); + //Setting CPLT_CTRL0 register value + l_data64.flush<0>(); + //CPLT_CTRL0.CTRL_CC_ABSTCLK_MUXSEL_DC = 1 + l_data64.writeBit(1); + //CPLT_CTRL0.TC_UNIT_SYNCCLK_MUXSEL_DC = 1 + l_data64.writeBit(1); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_CPLT_CTRL0_CLEAR, l_data64)); + + FAPI_DBG("Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief will force all chiplets out of flush +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_mem_startclocks_flushmode( + const fapi2::Target& i_target_chiplet) { + fapi2::buffer l_data64; FAPI_DBG("Entering ..."); + FAPI_INF("Clear flush_inhibit to go in to flush mode"); + //Setting CPLT_CTRL0 register value + l_data64.flush<0>(); + //CPLT_CTRL0.CTRL_CC_FLUSHMODE_INH_DC = 0 + l_data64.setBit(); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_CPLT_CTRL0_CLEAR, l_data64)); + FAPI_DBG("Exiting ..."); - return fapi2::FAPI2_RC_SUCCESS; +fapi_try_exit: + return fapi2::current_err; } diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_mem_startclocks.H b/src/import/chips/p9/procedures/hwp/perv/p9_mem_startclocks.H index 30361843b..f41132e5e 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_mem_startclocks.H +++ b/src/import/chips/p9/procedures/hwp/perv/p9_mem_startclocks.H @@ -7,7 +7,7 @@ /* */ /* EKB Project */ /* */ -/* COPYRIGHT 2015 */ +/* COPYRIGHT 2015,2016 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -21,11 +21,11 @@ /// /// @brief Start clocks on MBA/MCAs //------------------------------------------------------------------------------ -// *HWP HW Owner : Anusha Reddy Rangareddygari +// *HWP HW Owner : Abhishek Agarwal // *HWP HW Backup Owner : Srinivas V Naga -// *HWP FW Owner : Sunil Kumar +// *HWP FW Owner : Sunil kumar // *HWP Team : Perv -// *HWP Level : 1 +// *HWP Level : 2 // *HWP Consumed by : HB //------------------------------------------------------------------------------ @@ -37,15 +37,24 @@ #include -typedef fapi2::ReturnCode (*p9_mem_startclocks_FP_t)(const fapi2::Target&); +typedef fapi2::ReturnCode (*p9_mem_startclocks_FP_t)( + const fapi2::Target&); -/// @brief Drop fences and tholds on MBA/MCAs +/// @brief --drop vital fence +/// --reset abstclk muxsel and syncclk muxsel +/// --Module align chiplets +/// --Module clock start stop +/// --Check clock stat SL, NSL , ARY +/// --drop chiplet fence +/// --check checkstop register +/// --clear flush inhibit to go into flush mode /// -/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PROC_CHIP target +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target /// @return FAPI2_RC_SUCCESS if success, else error code. extern "C" { - fapi2::ReturnCode p9_mem_startclocks(const fapi2::Target& i_target_chiplet); + fapi2::ReturnCode p9_mem_startclocks(const + fapi2::Target& i_target_chip); } #endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_mem_startclocks.mk b/src/import/chips/p9/procedures/hwp/perv/p9_mem_startclocks.mk index 51a7e9a50..8a1445019 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_mem_startclocks.mk +++ b/src/import/chips/p9/procedures/hwp/perv/p9_mem_startclocks.mk @@ -7,7 +7,7 @@ # # EKB Project # -# COPYRIGHT 2015 +# COPYRIGHT 2015,2016 # [+] International Business Machines Corp. # # @@ -17,4 +17,5 @@ # # IBM_PROLOG_END_TAG PROCEDURE=p9_mem_startclocks +OBJS+=p9_sbe_common.o $(call BUILD_PROCEDURE) -- cgit v1.2.1