From 37931b3b0f8f291696059c8b42dc558cfe3c3719 Mon Sep 17 00:00:00 2001 From: Joe McGill Date: Thu, 15 Dec 2016 00:12:48 -0600 Subject: Add MSS customization support from CRP0 Lx MVPD Keyword V0 offsets are the same as V1 Move bad-bits error processing to 1.03 Change-Id: I233b3142ea8e8b08621b88a4b3af5417bbde5745 Original-Change-Id: I01e44c83f775b77e4ecc7afd7a5d92db524dfc98 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34073 Dev-Ready: Joseph J. McGill Tested-by: Jenkins Server Tested-by: PPE CI Reviewed-by: Martin Gloff Reviewed-by: Daniel M. Crowell Tested-by: Hostboot CI Reviewed-by: Matt K. Light Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58313 --- src/import/chips/p9/procedures/hwp/memory/tests/p9_mss_ut.mk | 1 + 1 file changed, 1 insertion(+) diff --git a/src/import/chips/p9/procedures/hwp/memory/tests/p9_mss_ut.mk b/src/import/chips/p9/procedures/hwp/memory/tests/p9_mss_ut.mk index 48e9a21e1..c58ce4318 100644 --- a/src/import/chips/p9/procedures/hwp/memory/tests/p9_mss_ut.mk +++ b/src/import/chips/p9/procedures/hwp/memory/tests/p9_mss_ut.mk @@ -50,6 +50,7 @@ $(WRAPPER)_DEPLIBS+=p9_mss_freq_drift $(WRAPPER)_DEPLIBS+=p9_mss_scominit $(WRAPPER)_DEPLIBS+=p9_mss_thermal_init $(WRAPPER)_DEPLIBS+=p9_mss_throttle_mem +$(WRAPPER)_DEPLIBS+=p9_mss_attr_update # USELIBS to get the header, DEPLIBS to get the so $(WRAPPER)_USELIBS+=p9_getecid -- cgit v1.2.1