From 30de5c86983e95543378e37a2320979a7f11bfce Mon Sep 17 00:00:00 2001 From: Chris Steffen Date: Fri, 12 Oct 2018 09:38:50 -0500 Subject: DMI Increase FIFO Margin - Increase Final L2U Delay from 1->2 - This will allow for greater freq mismatch between proc + centaur Change-Id: I1d70beba7205bfec404433e0f3dbaa75ed6363ab CQ: SW445095 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67417 Reviewed-by: Kevin F. Reick Tested-by: Jenkins Server Tested-by: Hostboot CI Reviewed-by: John G. Rell III Reviewed-by: Jennifer A. Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67425 Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Christian R. Geddes --- src/import/chips/p9/procedures/hwp/initfiles/p9c_dmi_io_scom.C | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9c_dmi_io_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9c_dmi_io_scom.C index 089236965..90b99acde 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9c_dmi_io_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9c_dmi_io_scom.C @@ -56,7 +56,6 @@ constexpr uint64_t literal_0b01 = 0b01; constexpr uint64_t literal_0b00 = 0b00; constexpr uint64_t literal_0b0010111 = 0b0010111; constexpr uint64_t literal_0b00010 = 0b00010; -constexpr uint64_t literal_0b0001 = 0b0001; constexpr uint64_t literal_0b0010 = 0b0010; constexpr uint64_t literal_0b0010001 = 0b0010001; constexpr uint64_t literal_0b0011000 = 0b0011000; @@ -4286,7 +4285,7 @@ fapi2::ReturnCode p9c_dmi_io_scom(const fapi2::Target& T if (l_def_IS_HW) { - l_scom_buffer.insert<52, 4, 60, uint64_t>(literal_0b0001 ); + l_scom_buffer.insert<52, 4, 60, uint64_t>(literal_0b0010 ); } else if (l_def_IS_SIM) { -- cgit v1.2.1