From 0f184fd25fdba313529897a6f0198c3d16893756 Mon Sep 17 00:00:00 2001 From: Joachim Fenkes Date: Mon, 4 Apr 2016 17:51:23 +0200 Subject: Add p9_proc_gettracearray procedure Generic procedure to dump a trace array. The API is similar to the P8 procedure, but the procedure takes trace _bus_ IDs as opposed to trace _array_ IDs and uses these to check the trace array's primary trace MUXes prior to dumping. There is also a flag to skip this check if you want to dump a specific trace array no matter which bus is muxed into it. The FAPI2 target supplied must match the trace array; most will just need a TARGET_TYPE_PROC_CHIP target, but some are targeted at OBUS, MCBIST, EX or CORE granularity. There's an inline function proc_gettracearray_target_type() that will help determine the target type. Change-Id: I0e3b26229cb81288c99ae229780d78039c1215bd Original-Change-Id: I093cd03bc90fbe93ed8fff3d18cd0676359fa5d1 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22847 Dev-Ready: Joachim Fenkes Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Joseph J. McGill Reviewed-by: Jenny Huynh Reviewed-by: Thi N. Tran Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40869 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell --- .../p9/procedures/hwp/perv/p9_proc_gettracearray.C | 333 +++++++++++++++++++++ .../p9/procedures/hwp/perv/p9_proc_gettracearray.H | 279 +++++++++++++++++ .../procedures/hwp/perv/p9_proc_gettracearray.mk | 27 ++ 3 files changed, 639 insertions(+) create mode 100644 src/import/chips/p9/procedures/hwp/perv/p9_proc_gettracearray.C create mode 100644 src/import/chips/p9/procedures/hwp/perv/p9_proc_gettracearray.H create mode 100644 src/import/chips/p9/procedures/hwp/perv/p9_proc_gettracearray.mk diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_proc_gettracearray.C b/src/import/chips/p9/procedures/hwp/perv/p9_proc_gettracearray.C new file mode 100644 index 000000000..079290090 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_proc_gettracearray.C @@ -0,0 +1,333 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/perv/p9_proc_gettracearray.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_proc_gettracearray.C +/// +/// @brief Collect contents of specified trace array via SCOM. +/// +/// Collects contents of specified trace array via SCOM. Optionally +/// manages chiplet domain trace engine state (start/stop/reset) around +/// trace array data collection. Trace array data can be collected only +/// when its controlling chiplet trace engine is stopped. +/// +/// Trace array entries will be packed into data buffer from +/// oldest->youngest entry. +/// +/// Calling code is expected to pass the proper target type based on the +/// desired trace resource; a convenience function is provided to find out +/// the expected target type for a given trace resource. +//------------------------------------------------------------------------------ +// *HWP HW Owner : Joachim Fenkes +// *HWP HW Backup Owner : Joe McGill +// *HWP FW Owner : Thi Tran +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : FSP +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include "p9_proc_gettracearray.H" + +#include +#include +#include +#include +#include +#include +#include + +//------------------------------------------------------------------------------ +// Constant definitions +//------------------------------------------------------------------------------ + +// offset to store high/low data within a given entry +const uint32_t HI_BIT_OFFSET = 0; +const uint32_t LO_BIT_OFFSET = 64; + +const uint32_t DEBUG_TRACE_CONTROL_OFS = PERV_DEBUG_TRACE_CONTROL - PERV_DBG_MODE_REG; + +const uint32_t DEBUG_TRACE_CONTROL_START = 0; +const uint32_t DEBUG_TRACE_CONTROL_STOP = 1; +const uint32_t DEBUG_TRACE_CONTROL_RESET = 2; + +const uint32_t TRACE_HI_DATA_OFS = + PERV_TP_TPCHIP_TRA0_TR0_TRACE_HI_DATA_REG - PERV_TP_TPCHIP_TRA0_TR0_TRACE_HI_DATA_REG; +const uint32_t TRACE_LO_DATA_OFS = + PERV_TP_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG - PERV_TP_TPCHIP_TRA0_TR0_TRACE_HI_DATA_REG; +const uint32_t TRACE_TRCTRL_CONFIG_OFS = + PERV_TP_TPCHIP_TRA0_TR0_TRACE_TRCTRL_CONFIG - PERV_TP_TPCHIP_TRA0_TR0_TRACE_HI_DATA_REG; + +const uint32_t EX_L21_SCOM_OFFSET = EQ_TPLC21_TR0_TRACE_HI_DATA_REG - EQ_TPLC20_TR0_TRACE_HI_DATA_REG; +const uint32_t EX_L31_SCOM_OFFSET = EQ_L3TRA1_TR0_TRACE_HI_DATA_REG - EQ_L3TRA0_TR0_TRACE_HI_DATA_REG; + +const uint32_t TRACE_LO_DATA_RUNNING = PERV_1_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG_RUNNING; +const uint32_t TRCTRL_MUX0_SEL = 14; +const uint32_t TRCTRL_MUX0_SEL_LEN = 2; + +const uint32_t TRACE_MUX_POSITIONS = 1 << TRCTRL_MUX0_SEL_LEN; + +//------------------------------------------------------------------------------ +// Table of known trace arrays +//------------------------------------------------------------------------------ + +struct ta_def +{ + /* One entry per mux setting; value of 0 means N/A */ + proc_gettracearray_bus_id bus_ids[TRACE_MUX_POSITIONS]; + uint32_t debug_scom_base, trace_scom_base, ex_odd_scom_offset; +}; + +proc_gettracearray_bus_id NO_TB = (proc_gettracearray_bus_id)0; + +static const ta_def ta_defs[] = +{ + /* PERV */ + { { PROC_TB_PIB, PROC_TB_OCC, PROC_TB_TOD }, PERV_TP_DBG_MODE_REG, PERV_TP_TPCHIP_TRA0_TR0_TRACE_HI_DATA_REG }, + { { PROC_TB_SBE, PROC_TB_PIB_ALT }, PERV_TP_DBG_MODE_REG, PERV_TP_TPCHIP_TRA0_TR1_TRACE_HI_DATA_REG }, + /* N0 */ + { { PROC_TB_PBIOE0 }, PU_N0_DBG_MODE_REG, PU_TCN0_TRA0_TR0_TRACE_HI_DATA_REG }, + { { PROC_TB_PBIOE1 }, PU_N0_DBG_MODE_REG, PU_TCN0_TRA0_TR1_TRACE_HI_DATA_REG }, + { { PROC_TB_CXA0, PROC_TB_NX }, PU_N0_DBG_MODE_REG, PU_TCN0_TRA1_TR0_TRACE_HI_DATA_REG }, + /* N1 */ + { { PROC_TB_PB6 }, PU_N1_DBG_MODE_REG, PU_TCN1_TRA0_TR0_TRACE_HI_DATA_REG }, + { { PROC_TB_PB7 }, PU_N1_DBG_MODE_REG, PU_TCN1_TRA0_TR1_TRACE_HI_DATA_REG }, + { { PROC_TB_PB8 }, PU_N1_DBG_MODE_REG, PU_TCN1_TRA1_TR0_TRACE_HI_DATA_REG }, + { { PROC_TB_PB9 }, PU_N1_DBG_MODE_REG, PU_TCN1_TRA1_TR1_TRACE_HI_DATA_REG }, + { { PROC_TB_PB10 }, PU_N1_DBG_MODE_REG, PU_TCN1_TRA2_TR0_TRACE_HI_DATA_REG }, + { { PROC_TB_PB11 }, PU_N1_DBG_MODE_REG, PU_TCN1_TRA2_TR1_TRACE_HI_DATA_REG }, + { { PROC_TB_MCD0, PROC_TB_MCD1, PROC_TB_VAS }, PU_N1_DBG_MODE_REG, PU_TCN1_TRA3_TR0_TRACE_HI_DATA_REG }, + { { PROC_TB_MCS2, PROC_TB_MCS3, PROC_TB_PB13 }, PU_N1_DBG_MODE_REG, PU_TCN1_TRA3_TR1_TRACE_HI_DATA_REG }, + { { PROC_TB_PBIO0 }, PU_N1_DBG_MODE_REG, PU_TCN1_TRA4_TR0_TRACE_HI_DATA_REG }, + { { PROC_TB_PBIO1 }, PU_N1_DBG_MODE_REG, PU_TCN1_TRA4_TR1_TRACE_HI_DATA_REG }, + /* N2 */ + { { PROC_TB_CXA1, PROC_TB_IOPSI }, PU_N2_DBG_MODE_REG, PU_TCN2_TRA0_TR0_TRACE_HI_DATA_REG }, + { { PROC_TB_PCIS0, PROC_TB_PCIS1, PROC_TB_PCIS2 }, PU_N2_DBG_MODE_REG, PU_TCN2_TRA0_TR1_TRACE_HI_DATA_REG }, + /* N3 */ + { { PROC_TB_PB0 }, PU_N3_DBG_MODE_REG, PU_TCN3_TRA0_TR0_TRACE_HI_DATA_REG }, + { { PROC_TB_PB1 }, PU_N3_DBG_MODE_REG, PU_TCN3_TRA0_TR1_TRACE_HI_DATA_REG }, + { { PROC_TB_PB2 }, PU_N3_DBG_MODE_REG, PU_TCN3_TRA1_TR0_TRACE_HI_DATA_REG }, + { { PROC_TB_PB3 }, PU_N3_DBG_MODE_REG, PU_TCN3_TRA1_TR1_TRACE_HI_DATA_REG }, + { { PROC_TB_PB4 }, PU_N3_DBG_MODE_REG, PU_TCN3_TRA2_TR0_TRACE_HI_DATA_REG }, + { { PROC_TB_PB5 }, PU_N3_DBG_MODE_REG, PU_TCN3_TRA2_TR1_TRACE_HI_DATA_REG }, + { { PROC_TB_INT, PROC_TB_NPU1, PROC_TB_NMMU1 }, PU_N3_DBG_MODE_REG, PU_TCN3_TRA3_TR0_TRACE_HI_DATA_REG }, + { { PROC_TB_MCS0, PROC_TB_MCS1, PROC_TB_PB12 }, PU_N3_DBG_MODE_REG, PU_TCN3_TRA3_TR1_TRACE_HI_DATA_REG }, + { { PROC_TB_BRIDGE }, PU_N3_DBG_MODE_REG, PU_TCN3_TRA4_TR0_TRACE_HI_DATA_REG }, + { { PROC_TB_NPU0 }, PU_N3_DBG_MODE_REG, PU_TCN3_TRA5_TR0_TRACE_HI_DATA_REG }, + { { PROC_TB_NMMU0 }, PU_N3_DBG_MODE_REG, PU_TCN3_TRA5_TR1_TRACE_HI_DATA_REG }, + /* XBUS */ + { { PROC_TB_PBIOX0, PROC_TB_IOX0 }, XBUS_PERV_DBG_MODE_REG, XBUS_PERV_TCXB_TRA0_TR0_TRACE_HI_DATA_REG }, + { { PROC_TB_PBIOX1, PROC_TB_IOX1 }, XBUS_PERV_DBG_MODE_REG, XBUS_PERV_TCXB_TRA0_TR1_TRACE_HI_DATA_REG }, + { { PROC_TB_PBIOX2, PROC_TB_IOX2 }, XBUS_PERV_DBG_MODE_REG, XBUS_PERV_TCXB_TRA1_TR0_TRACE_HI_DATA_REG }, + /* PCIx */ + { { PROC_TB_PCI0X, PROC_TB_PCI00 }, PEC_0_DBG_MODE_REG, PEC_0_TCPCI0_TRA0_TR0_TRACE_HI_DATA_REG }, + { { PROC_TB_PCI1X, PROC_TB_PCI11, PROC_TB_PCI12 }, PEC_1_DBG_MODE_REG, PEC_1_TCPCI1_TRA0_TR0_TRACE_HI_DATA_REG }, + { { PROC_TB_PCI2X, PROC_TB_PCI23, PROC_TB_PCI24, PROC_TB_PCI25 }, PEC_2_DBG_MODE_REG, PEC_2_TCPCI2_TRA0_TR0_TRACE_HI_DATA_REG }, + /* OBUS */ + { { PROC_TB_PBIOOA, PROC_TB_IOO }, OBUS_TCOB0_DBG_MODE_REG, OBUS_TCOB0_TRA0_TR0_TRACE_HI_DATA_REG }, + /* MC */ + { { PROC_TB_MCA0 }, MCA_3_DBG_MODE_REG, PU_TCMC01_FAST_TRA0_TRACE_HI_DATA_REG }, + { { PROC_TB_MCA1 }, MCA_3_DBG_MODE_REG, PU_TCMC01_FAST_TRA1_TRACE_HI_DATA_REG }, + { { PROC_TB_IOMC0, PROC_TB_IOMC1, PROC_TB_IOMC2, PROC_TB_IOMC3 }, MCA_3_DBG_MODE_REG, MCA_TCMC01_SLOW_TRA0_TRACE_HI_DATA_REG }, + /* EX */ + { { PROC_TB_L20, NO_TB, NO_TB, PROC_TB_SKIT10 }, EQ_DBG_MODE_REG, EQ_TPLC20_TR0_TRACE_HI_DATA_REG, EX_L21_SCOM_OFFSET }, + { { PROC_TB_L21, NO_TB, NO_TB, PROC_TB_SKIT11 }, EQ_DBG_MODE_REG, EQ_TPLC20_TR1_TRACE_HI_DATA_REG, EX_L21_SCOM_OFFSET }, + { { PROC_TB_L30, PROC_TB_NCU0, PROC_TB_CME, PROC_TB_EQPB }, EQ_DBG_MODE_REG, EQ_L3TRA0_TR0_TRACE_HI_DATA_REG, EX_L31_SCOM_OFFSET }, + { { PROC_TB_L31, PROC_TB_NCU1, PROC_TB_IVRM, PROC_TB_SKEWADJ }, EQ_DBG_MODE_REG, EQ_L3TRA0_TR1_TRACE_HI_DATA_REG, EX_L31_SCOM_OFFSET }, + /* CORE */ + { { PROC_TB_CORE0 }, C_DBG_MODE_REG, 0x00011440 }, + { { PROC_TB_CORE1 }, C_DBG_MODE_REG, 0x00011480 }, +}; + +#define ARRAY_SIZE(array) (sizeof(array) / sizeof(array[0])) + +class TraceArrayFinder +{ + public: + const ta_def* pdef; + uint32_t mux_sel; + + TraceArrayFinder(proc_gettracearray_bus_id i_trace_bus) : pdef(NULL), mux_sel(0) + { + for (unsigned int i = 0; i < ARRAY_SIZE(ta_defs); i++) + { + for (uint32_t sel = 0; sel < TRACE_MUX_POSITIONS; sel++) + { + if (ta_defs[i].bus_ids[sel] == i_trace_bus) + { + pdef = ta_defs + i; + mux_sel = sel; + return; + } + } + } + } +}; + +//------------------------------------------------------------------------------ +// HWP entry point +//------------------------------------------------------------------------------ +extern "C" fapi2::ReturnCode p9_proc_gettracearray( + const fapi2::Target& i_target, + const proc_gettracearray_args& i_args, + fapi2::variable_buffer& o_ta_data) +{ + fapi2::Target < PROC_GETTRACEARRAY_TARGET_TYPES | fapi2::TARGET_TYPE_EQ > target = i_target; + uint32_t tra_scom_offset = 0; + + // mark HWP entry + FAPI_IMP("Entering ..."); + + const TraceArrayFinder l_ta_finder(i_args.trace_bus); + + if (!l_ta_finder.pdef) + { + FAPI_ERR("Unsupported trace bus identifier %d specified", i_args.trace_bus); + return fapi2::RC_PROC_GETTRACEARRAY_INVALID_BUS; + ; + } + + const uint32_t DEBUG_TRACE_CONTROL = l_ta_finder.pdef->debug_scom_base + DEBUG_TRACE_CONTROL_OFS; + const uint32_t TRACE_SCOM_BASE = l_ta_finder.pdef->trace_scom_base; + + fapi2::TargetType arg_type = i_target.getType(); + fapi2::TargetType ta_type = proc_gettracearray_target_type(i_args.trace_bus); + + if ((arg_type & ta_type) == 0) + { + FAPI_ERR("Specified trace array requires target type 0x%X, but the supplied target is of type 0x%X", ta_type, arg_type); + return fapi2::RC_PROC_GETTRACEARRAY_INVALID_TARGET; + } + + /* Nimbus DD1 core traces can't be read out via SCOM. Check an EC feature to see if that's fixed. */ + if (ta_type == fapi2::TARGET_TYPE_CORE) + { + uint8_t l_core_trace_scomable = 0; + + fapi2::Target proc_target = i_target.getParent(); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_CORE_TRACE_SCOMABLE, proc_target, l_core_trace_scomable), + "Failed to query chip EC feature ATTR_CHIP_EC_FEATURE_CORE_TRACE_SCOMABLE"); + + if (!l_core_trace_scomable) + { + FAPI_ERR("Core arrays cannot be dumped in this chip EC; please use fastarray instead."); + return fapi2::RC_PROC_GETTRACEARRAY_CORE_NOT_DUMPABLE; + } + } + + /* For convenience, we link Cache trace arrays to the virtual EX chiplets. Transform back + * to EQ chiplet and SCOM address offset. */ + if (ta_type == fapi2::TARGET_TYPE_EX) + { + uint8_t l_chipunit_num; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_target, l_chipunit_num), + "Failed to get chipUnit ID from EX target"); + target = i_target.getParent(); + + if (l_chipunit_num & 1) + { + tra_scom_offset = l_ta_finder.pdef->ex_odd_scom_offset; + } + } + + /* Check that the trace mux is set up as expected */ + if (!i_args.ignore_mux_setting) + { + fapi2::buffer buf; + FAPI_TRY(fapi2::getScom(target, TRACE_SCOM_BASE + tra_scom_offset + TRACE_TRCTRL_CONFIG_OFS, buf), + "Failed to read current trace mux setting"); + uint32_t cur_sel = 0; + buf.extractToRight(cur_sel); + + if (cur_sel != l_ta_finder.mux_sel) + { + FAPI_ERR("Primary trace mux is set to %d, but %d is needed for requested trace bus", cur_sel, l_ta_finder.mux_sel); + return fapi2::RC_PROC_GETTRACEARRAY_TRACE_MUX_INCORRECT; + } + } + + if (i_args.stop_pre_dump) + { + FAPI_DBG("Stopping trace arrays"); + fapi2::buffer buf; + buf.flush<0>().setBit(); + FAPI_TRY(fapi2::putScom(target, DEBUG_TRACE_CONTROL, buf), "Failed to stop chiplet domain trace arrays"); + } + + if (i_args.collect_dump) + { + fapi2::buffer buf; + o_ta_data.resize(PROC_GETTRACEARRAY_NUM_ENTRIES * PROC_GETTRACEARRAY_BITS_PER_ENTRY).flush<0>(); + + /* Start with the low data register because that's where the "trace running" bit is. */ + for (int i = 0; i < PROC_GETTRACEARRAY_NUM_ENTRIES; i++) + { + FAPI_TRY(fapi2::getScom(target, TRACE_SCOM_BASE + tra_scom_offset + TRACE_LO_DATA_OFS, buf), + "Failed to read trace array low data register, iteration %d", i); + + /* The "trace running" bit is our best indicator of whether the array is currently running. + * If it is, the read won't have incremented the address, so it's okay to bail out. */ + if (buf.getBit()) + { + FAPI_ERR("Trace array is still running -- If you think you stopped it, maybe the controlling debug macro is slaved to another debug macro?"); + return fapi2::RC_PROC_GETTRACEARRAY_TRACE_RUNNING; + } + + FAPI_TRY(o_ta_data.set(buf, 2 * i + 1), "Failed to insert data into trace buffer"); + } + + /* Then dump the high data */ + for (int i = 0; i < PROC_GETTRACEARRAY_NUM_ENTRIES; i++) + { + FAPI_TRY(fapi2::getScom(target, TRACE_SCOM_BASE + tra_scom_offset + TRACE_HI_DATA_OFS, buf), + "Failed to read trace array high data register, iteration %d", i); + FAPI_TRY(o_ta_data.set(buf, 2 * i + 0), "Failed to insert data into trace buffer"); + } + } + + if (i_args.reset_post_dump) + { + FAPI_DBG("Resetting trace arrays"); + fapi2::buffer buf; + buf.flush<0>().setBit(); + FAPI_TRY(fapi2::putScom(target, DEBUG_TRACE_CONTROL, buf), "Failed to reset chiplet domain trace arrays"); + } + + if (i_args.restart_post_dump) + { + FAPI_DBG("Starting trace arrays"); + fapi2::buffer buf; + buf.flush<0>().setBit(); + FAPI_TRY(fapi2::putScom(target, DEBUG_TRACE_CONTROL, buf), "Failed to restart chiplet domain trace arrays"); + } + + // mark HWP exit + FAPI_IMP("Success"); + return fapi2::FAPI2_RC_SUCCESS; + +fapi_try_exit: + return fapi2::current_err; +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_proc_gettracearray.H b/src/import/chips/p9/procedures/hwp/perv/p9_proc_gettracearray.H new file mode 100644 index 000000000..9ce6883b4 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_proc_gettracearray.H @@ -0,0 +1,279 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/perv/p9_proc_gettracearray.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_proc_gettracearray.H +/// +/// @brief Collect contents of specified trace array via SCOM. +/// +/// Collects contents of specified trace array via SCOM. Optionally +/// manages chiplet domain trace engine state (start/stop/reset) around +/// trace array data collection. Trace array data can be collected only +/// when its controlling chiplet trace engine is stopped. +/// +/// Trace array entries will be packed into data buffer from +/// oldest->youngest entry. +/// +/// Calling code is expected to pass the proper target type based on the +/// desired trace resource; a convenience function is provided to find out +/// the expected target type for a given trace resource. +//------------------------------------------------------------------------------ +// *HWP HW Owner : Joachim Fenkes +// *HWP HW Backup Owner : Joe McGill +// *HWP FW Owner : Thi Tran +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : FSP +//------------------------------------------------------------------------------ + +#ifndef _PROC_GETTRACEARRAY_H_ +#define _PROC_GETTRACEARRAY_H_ + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ + +#include + +//------------------------------------------------------------------------------ +// Constant definitions +//------------------------------------------------------------------------------ + +// maximum trace array entries supported by P9 chip design +const uint8_t PROC_GETTRACEARRAY_NUM_ENTRIES = 128; +// bits to store per trace array entry +const uint8_t PROC_GETTRACEARRAY_BITS_PER_ENTRY = 128; + + +//------------------------------------------------------------------------------ +// Structure definitions +//------------------------------------------------------------------------------ + +/** + * @brief Identifiers for supported trace arrays. + * + * There is an identifier for each available trace bus. Many arrays are shared + * between multiple trace buses; in that case, several identifiers point to the + * same trace array. + */ +enum proc_gettracearray_bus_id +{ + /* Pervasive chiplet - TARGET_TYPE_PROC_CHIP */ + PROC_TB_PIB = 1, + PROC_TB_OCC, + PROC_TB_TOD, + PROC_TB_SBE, + PROC_TB_PIB_ALT, /* alternate sink for PIB trace */ + + /* Nest chiplets - TARGET_TYPE_PROC_CHIP */ + PROC_TB_PB0, + PROC_TB_PB1, + PROC_TB_PB2, + PROC_TB_PB3, + PROC_TB_PB4, + PROC_TB_PB5, + PROC_TB_PB6, + PROC_TB_PB7, + PROC_TB_PB8, + PROC_TB_PB9, + PROC_TB_PB10, + PROC_TB_PB11, + PROC_TB_PB12, + PROC_TB_PB13, + PROC_TB_MCS0, + PROC_TB_MCS1, + PROC_TB_MCS2, + PROC_TB_MCS3, + PROC_TB_MCD0, + PROC_TB_MCD1, + PROC_TB_VAS, + PROC_TB_PBIO0, + PROC_TB_PBIO1, + PROC_TB_PBIOE0, + PROC_TB_PBIOE1, + PROC_TB_CXA0, + PROC_TB_CXA1, + PROC_TB_NX, + PROC_TB_IOPSI, + PROC_TB_PCIS0, + PROC_TB_PCIS1, + PROC_TB_PCIS2, + PROC_TB_NPU0, + PROC_TB_NPU1, + PROC_TB_NMMU0, + PROC_TB_NMMU1, + PROC_TB_INT, + PROC_TB_BRIDGE, + + /* XBUS chiplet - TARGET_TYPE_PROC_CHIP */ + PROC_TB_IOX0, + PROC_TB_IOX1, + PROC_TB_IOX2, + PROC_TB_PBIOX0, + PROC_TB_PBIOX1, + PROC_TB_PBIOX2, + + /* PCI chiplets - TARGET_TYPE_PROC_CHIP */ + PROC_TB_PCI0X, + PROC_TB_PCI00, + PROC_TB_PCI1X, + PROC_TB_PCI11, + PROC_TB_PCI12, + PROC_TB_PCI2X, + PROC_TB_PCI23, + PROC_TB_PCI24, + PROC_TB_PCI25, + + _PROC_TB_LAST_PROC_TARGET = PROC_TB_PCI25, + + /* OBus chiplets - TARGET_TYPE_OBUS */ + PROC_TB_PBIOOA, + PROC_TB_IOO, + + _PROC_TB_LAST_OBUS_TARGET = PROC_TB_IOO, + + /* MemCtrl chiplets - TARGET_TYPE_MCS */ + PROC_TB_MCA0, + PROC_TB_MCA1, + PROC_TB_IOMC0, + PROC_TB_IOMC1, + PROC_TB_IOMC2, + PROC_TB_IOMC3, + + _PROC_TB_LAST_MC_TARGET = PROC_TB_IOMC3, + + /* Cache chiplets - TARGET_TYPE_EX */ + PROC_TB_L30, + PROC_TB_L31, + PROC_TB_NCU0, + PROC_TB_NCU1, + PROC_TB_CME, + PROC_TB_EQPB, // note: only for odd EX instances + PROC_TB_IVRM, + PROC_TB_SKEWADJ, // note: only for even EX instances + PROC_TB_L20, + PROC_TB_L21, + PROC_TB_SKIT10, + PROC_TB_SKIT11, + + _PROC_TB_LAST_EX_TARGET = PROC_TB_SKIT11, + + /* Core chiplets - TARGET_TYPE_CORE */ + PROC_TB_CORE0, + PROC_TB_CORE1, +}; + +static const fapi2::TargetType PROC_GETTRACEARRAY_TARGET_TYPES = + fapi2::TARGET_TYPE_PROC_CHIP | + fapi2::TARGET_TYPE_OBUS | + fapi2::TARGET_TYPE_MCBIST | + fapi2::TARGET_TYPE_EX | + fapi2::TARGET_TYPE_CORE; + +// structure to represent HWP arguments +struct proc_gettracearray_args +{ + proc_gettracearray_bus_id trace_bus; ///< The trace bus whose associated trace array should be dumped + bool stop_pre_dump; ///< Stop the trace array before starting the dump + bool ignore_mux_setting; ///< Do not fail if the primary trace mux is set to a different bus + bool collect_dump; ///< Do dump the trace array; useful if you just want to start/stop + bool reset_post_dump; ///< Reset the debug logic after dumping + bool restart_post_dump; ///< Start the trace array after dumping +}; + +// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode +(*p9_proc_gettracearray_FP_t)(const fapi2::Target&, + const proc_gettracearray_args&, + fapi2::variable_buffer& o_ta_data); + +extern "C" +{ + + /** + * @brief Return the target type needed to access a given trace array + * @param ta_id The trace array / trace bus ID requested. + * @return The type of target to hand to proc_gettracearray to clearly identify the array instance. + */ + static inline fapi2::TargetType proc_gettracearray_target_type(proc_gettracearray_bus_id i_trace_bus) + { + if (i_trace_bus <= _PROC_TB_LAST_PROC_TARGET) + { + return fapi2::TARGET_TYPE_PROC_CHIP; + } + else if (i_trace_bus <= _PROC_TB_LAST_OBUS_TARGET) + { + return fapi2::TARGET_TYPE_OBUS; + } + else if (i_trace_bus <= _PROC_TB_LAST_MC_TARGET) + { + return fapi2::TARGET_TYPE_MCBIST; + } + else if (i_trace_bus <= _PROC_TB_LAST_EX_TARGET) + { + return fapi2::TARGET_TYPE_EX; + } + else + { + return fapi2::TARGET_TYPE_CORE; + } + } + +//------------------------------------------------------------------------------ +// Function prototype +//------------------------------------------------------------------------------ + + /** + * @brief Retrieve trace array data from selected trace array via SCOM, + * optionally performing trace stop (prior to dump) and/or + * trace restart (after dump) + * + * @param i_target Chip or chiplet target. The necessary target type can be + * queried through proc_gettracearray_target_type(). + * @param i_args Argument structure with additional parameters + * @param o_ta_data Trace array data. Will contain all trace entries read + * from the array concatenated, starting with the oldest trace + * entry and ending with the newest. + * @return FAPI2_RC_SUCCESS + * if trace array dump sequence completes successfully, + * RC_PROC_GETTRACEARRAY_INVALID_BUS + * if an invalid trace bus ID has been requested + * RC_PROC_GETTRACEARRAY_INVALID_TARGET + * if the supplied target type does not match the requested trace bus + * RC_PROC_GETTRACEARRAY_CORE_NOT_DUMPABLE + * if a core trace array has been requested but the chip's core + * is not dumpable via SCOM -> use fastarray instead + * RC_PROC_GETTRACEARRAY_TRACE_RUNNING + * if trace array is running when dump collection is attempted, + * RC_PROC_GETTRACEARRAY_TRACE_MUX_INCORRECT + * if the primary trace mux is not set up to trace the requested bus, + * else FAPI getscom/putscom return code for failing operation + */ + fapi2::ReturnCode p9_proc_gettracearray(const fapi2::Target& i_target, + const proc_gettracearray_args& i_args, + fapi2::variable_buffer& o_ta_data); + +} // extern "C" + +#endif // _PROC_GETTRACEARRAY_H_ diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_proc_gettracearray.mk b/src/import/chips/p9/procedures/hwp/perv/p9_proc_gettracearray.mk new file mode 100644 index 000000000..4a10260c8 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_proc_gettracearray.mk @@ -0,0 +1,27 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/import/chips/p9/procedures/hwp/perv/p9_proc_gettracearray.mk $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2015,2017 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +PROCEDURE=p9_proc_gettracearray +lib$(PROCEDURE)_DEPLIBS=fapi2_utils +$(call BUILD_PROCEDURE) -- cgit v1.2.1