From 067163534e2acd38d47bf45378bb90c875f5dc43 Mon Sep 17 00:00:00 2001 From: Ben Gass Date: Tue, 14 Feb 2017 03:06:01 -0600 Subject: Updating NV scom address xlate for dd2. Change-Id: I7d6dea78895807554b692f3ca9696a3de2ba8986 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36411 Tested-by: Jenkins Server Tested-by: Hostboot CI Dev-Ready: Brent Wieman Reviewed-by: Brent Wieman Reviewed-by: Daniel M. Crowell Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36428 Tested-by: FSP CI Jenkins --- src/import/chips/p9/common/scominfo/p9_cu.H | 3 +- src/import/chips/p9/common/scominfo/p9_scominfo.C | 167 +++++++++++++++++++--- src/import/chips/p9/common/scominfo/p9_scominfo.H | 11 +- src/usr/scom/scomtrans.C | 83 ++++++++++- src/usr/scom/scomtrans.H | 9 ++ 5 files changed, 251 insertions(+), 22 deletions(-) diff --git a/src/import/chips/p9/common/scominfo/p9_cu.H b/src/import/chips/p9/common/scominfo/p9_cu.H index b70a12f86..15c1f803f 100644 --- a/src/import/chips/p9/common/scominfo/p9_cu.H +++ b/src/import/chips/p9/common/scominfo/p9_cu.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -41,6 +41,7 @@ extern "C" { + /// P9 chip unit type enumeration typedef enum { diff --git a/src/import/chips/p9/common/scominfo/p9_scominfo.C b/src/import/chips/p9/common/scominfo/p9_scominfo.C index d2fcb6951..aa4cd06c4 100644 --- a/src/import/chips/p9/common/scominfo/p9_scominfo.C +++ b/src/import/chips/p9/common/scominfo/p9_scominfo.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -49,7 +49,7 @@ extern "C" //Used to help generate entries for the SCOMdef documentation, //These aren't general PIB addresses - if (i_mode == PPE_MODE) + if ((i_mode & PPE_MODE) == PPE_MODE) { switch (i_p9CU) { @@ -149,9 +149,57 @@ extern "C" break; case PU_NV_CHIPUNIT: - l_scom.set_sat_id((l_scom.get_sat_id() % 4) + ((i_chipUnitNum / 2) * 4)); - l_scom.set_sat_offset( (l_scom.get_sat_offset() % 32) + - (32 * (i_chipUnitNum % 2))); + if ((i_mode & P9N_DD1_SI_MODE) == P9N_DD1_SI_MODE) + { + l_scom.set_sat_id((l_scom.get_sat_id() % 4) + ((i_chipUnitNum / 2) * 4)); + l_scom.set_sat_offset( (l_scom.get_sat_offset() % 32) + + (32 * (i_chipUnitNum % 2))); + } + else + { + uint64_t l_sa = i_scomAddr; + + // rrrrrrSTIDxxx--- + // 000100 yyy + // x"4900" & "00" when "00100010", -- stk0, ntl0, 00-07, hyp-only + // x"0b00" & "11" when "00101001", -- stk0, ntl1, 24-31, user-acc + // STID + // x"5900" & "00" when "01100010", -- stk1, ntl0, 00-07, hyp-only + // x"1b00" & "11" when "01101001", -- stk1, ntl1, 24-31, user-acc + // STID + // x"6900" & "00" when "10100010", -- stk2, ntl0, 00-07, hyp-only + // x"2b00" & "11" when "10101001", -- stk2, ntl1, 24-31, user-acc + + if ((i_chipUnitNum / 2) == 0) + { + l_sa = (l_sa & 0xFFFFFFFFFFFF007FULL) | 0x0000000000001100ULL ; + } + + if ((i_chipUnitNum / 2) == 1) + { + l_sa = (l_sa & 0xFFFFFFFFFFFF007FULL) | 0x0000000000001300ULL ; + } + + if ((i_chipUnitNum / 2) == 2) + { + l_sa = (l_sa & 0xFFFFFFFFFFFF007FULL) | 0x0000000000001500ULL ; + } + + uint64_t l_eo = (l_sa & 0x71) >> 3; + + if (l_eo > 5 && (i_chipUnitNum % 2 == 0)) + { + l_sa -= 0x20ULL; // 0b100 000 + } + + if (l_eo <= 5 && (i_chipUnitNum % 2 == 1)) + { + l_sa += 0x20ULL; // 0b100 000 + } + + l_scom.set_addr(l_sa); + } + break; case PU_PEC_CHIPUNIT: @@ -338,7 +386,7 @@ extern "C" uint8_t l_sat_id = l_scom.get_sat_id(); uint8_t l_sat_offset = l_scom.get_sat_offset(); - if (i_mode == PPE_MODE) + if ((i_mode & PPE_MODE) == PPE_MODE) { if (PPE_EP00_CHIPLET_ID <= l_chiplet_id && l_chiplet_id <= PPE_EP05_CHIPLET_ID) @@ -514,18 +562,103 @@ extern "C" } // PU_NV_CHIPUNIT - // See npu_misc_regs.vhdl, line 2710, - // sc_addr(0 to 6) represents sat_id(0..3) and sat_offset(0..2) - // only stkX, ntlX registers are translated to NX target type - // nv: 0..5 - if ((l_chiplet_id == N3_CHIPLET_ID) && - (l_port == UNIT_PORT_ID) && - (((l_ring == N3_NPU_0_RING_ID) && ((l_sat_id % 4) == 3) && l_sat_id <= 11))) + if ((i_mode & P9N_DD1_SI_MODE) == P9N_DD1_SI_MODE) { - o_chipUnitRelated = true; - o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_NV_CHIPUNIT, - (2 * (l_sat_id / 4)) + - (l_sat_offset / 32))); + // See npu_misc_regs.vhdl, line 2710, + // sc_addr(0 to 6) represents sat_id(0..3) and sat_offset(0..2) + // only stkX, ntlX registers are translated to NX target type + // nv: 0..5 + if ((l_chiplet_id == N3_CHIPLET_ID) && + (l_port == UNIT_PORT_ID) && + (((l_ring == N3_NPU_0_RING_ID) && ((l_sat_id % 4) == 3) && l_sat_id <= 11))) + { + o_chipUnitRelated = true; + o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_NV_CHIPUNIT, + (2 * (l_sat_id / 4)) + + (l_sat_offset / 32))); + } + } + else + { + //DD2 NV link (and Cumulus until we know better) + // See npu_misc_regs.vhdl + // sc_addr(0 to 7) bits 1 to 4 are the sat_id bit 0 is the lsb of the ring + // rings 4 and 5 are used. + // rrrrrrSTIDxxx--- + // 000100 + // x"4900" & "00" when "00100010", -- stk0, ntl0, 00-07, hyp-only + // x"4900" & "01" when "00100011", -- stk0, ntl0, 08-15, hyp-only + // x"4900" & "10" when "00100100", -- stk0, ntl0, 16-23, hyp-only + // x"0900" & "11" when "00100101", -- stk0, ntl0, 24-31, user-acc + // x"4b00" & "00" when "00100110", -- stk0, ntl1, 00-07, hyp-only + // x"4b00" & "01" when "00100111", -- stk0, ntl1, 08-15, hyp-only + // x"4b00" & "10" when "00101000", -- stk0, ntl1, 16-23, hyp-only -- addresses 0x140-147 + // x"0b00" & "11" when "00101001", -- stk0, ntl1, 24-31, user-acc + // STID + // x"5900" & "00" when "01100010", -- stk1, ntl0, 00-07, hyp-only + // x"5900" & "01" when "01100011", -- stk1, ntl0, 08-15, hyp-only + // x"5900" & "10" when "01100100", -- stk1, ntl0, 16-23, hyp-only + // x"1900" & "11" when "01100101", -- stk1, ntl0, 24-31, user-acc + // x"5b00" & "00" when "01100110", -- stk1, ntl1, 00-07, hyp-only + // x"5b00" & "01" when "01100111", -- stk1, ntl1, 08-15, hyp-only + // x"5b00" & "10" when "01101000", -- stk1, ntl1, 16-23, hyp-only -- addresses 0x340-347 + // x"1b00" & "11" when "01101001", -- stk1, ntl1, 24-31, user-acc + // STID + // x"6900" & "00" when "10100010", -- stk2, ntl0, 00-07, hyp-only + // x"6900" & "01" when "10100011", -- stk2, ntl0, 08-15, hyp-only + // x"6900" & "10" when "10100100", -- stk2, ntl0, 16-23, hyp-only + // x"2900" & "11" when "10100101", -- stk2, ntl0, 24-31, user-acc + // x"6b00" & "00" when "10100110", -- stk2, ntl1, 00-07, hyp-only + // x"6b00" & "01" when "10100111", -- stk2, ntl1, 08-15, hyp-only + // x"6b00" & "10" when "10101000", -- stk2, ntl1, 16-23, hyp-only -- addresses 0x540-54f + // x"2b00" & "11" when "10101001", -- stk2, ntl1, 24-31, user-acc + if ((l_chiplet_id == N3_CHIPLET_ID) && + (l_port == UNIT_PORT_ID)) + { + + //We have to do ugly bit manipulation here anyway. It is clearer + //just to do it with the raw scom address. + //Combine the ring(6) sat_id(4) and high order 3 bits of sat_offset + //to compare with vhdl values for NV registers + uint64_t npuaddr = (i_scomAddr & 0xFFF8ULL) >> 3; + + if (0x0222ULL <= npuaddr && npuaddr <= 0x0225ULL) + { + o_chipUnitRelated = true; + o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_NV_CHIPUNIT, 0)); + } + + if (0x0226ULL <= npuaddr && npuaddr <= 0x0229ULL) + { + o_chipUnitRelated = true; + o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_NV_CHIPUNIT, 1)); + } + + if (0x0262ULL <= npuaddr && npuaddr <= 0x0265ULL) + { + o_chipUnitRelated = true; + o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_NV_CHIPUNIT, 2)); + } + + if (0x0266ULL <= npuaddr && npuaddr <= 0x0269ULL) + { + o_chipUnitRelated = true; + o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_NV_CHIPUNIT, 3)); + } + + if (0x02A2ULL <= npuaddr && npuaddr <= 0x02A5ULL) + { + o_chipUnitRelated = true; + o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_NV_CHIPUNIT, 4)); + } + + if (0x02A6ULL <= npuaddr && npuaddr <= 0x02A9ULL) + { + o_chipUnitRelated = true; + o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_NV_CHIPUNIT, 5)); + } + } + } // PU_PEC_CHIPUNIT (nest) diff --git a/src/import/chips/p9/common/scominfo/p9_scominfo.H b/src/import/chips/p9/common/scominfo/p9_scominfo.H index fdabb9f1c..38c74888a 100644 --- a/src/import/chips/p9/common/scominfo/p9_scominfo.H +++ b/src/import/chips/p9/common/scominfo/p9_scominfo.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -44,7 +44,12 @@ extern "C" { - static const uint32_t PPE_MODE = 1; + //Modes for scominfo functions + static const uint32_t P9N_DD1_SI_MODE = 0x0; + static const uint32_t PPE_MODE = 0x1; + static const uint32_t P9N_DD2_SI_MODE = 0x2; + static const uint32_t P9C_DD1_SI_MODE = 0x4; + static const uint32_t P9C_DD2_SI_MODE = 0x8; typedef enum { @@ -60,7 +65,7 @@ extern "C" /// @param[in] i_p9CU Enumeration of the chip unit type /// @param[in] i_chipUnitNum Instance number of the chip unit /// @param[in] i_scomAddr The input SCOM address associated with the chip unit type - /// @param[in] i_mode Used for special purposes, default to 0 + /// @param[in] i_mode Used for special purposes, default to 0 = p9n dd1, 1 = ppe_mode, 2 = p9n dd2, 4 = p9c dd1, 8 = p9c dd2 /// @retval uint64_t Actual SCOM address for the chip unit instance passed in uint64_t p9_scominfo_createChipUnitScomAddr(const p9ChipUnits_t i_p9CU, const uint8_t i_chipUnitNum, const uint64_t i_scomAddr, const uint32_t i_mode = 0); diff --git a/src/usr/scom/scomtrans.C b/src/usr/scom/scomtrans.C index 089b74ec2..518585f7f 100644 --- a/src/usr/scom/scomtrans.C +++ b/src/usr/scom/scomtrans.C @@ -304,6 +304,10 @@ errlHndl_t p9_translation (TARGETING::Target * &i_target, p9ChipUnits_t l_chipUnit = NONE; std::vector l_scomPairings; + //Need to pass the chip/ec level into the translate function + uint32_t l_chipLevel = getChipLevel(i_target); + l_chip_mode |= l_chipLevel; + //Make sure that scom addr is related to a chip unit uint32_t isChipUnitScomRC = p9_scominfo_isChipUnitScom(io_addr, @@ -552,8 +556,10 @@ errlHndl_t p9_translation (TARGETING::Target * &i_target, return l_err; } +////////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////////// bool getChipUnit (TARGETING::TYPE i_type, - p9ChipUnits_t &o_chipUnit) + p9ChipUnits_t &o_chipUnit) { bool l_isError = false; switch(i_type) @@ -656,6 +662,81 @@ bool getChipUnit (TARGETING::TYPE i_type, } +////////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////////// +/** + * @brief Computes the chip/ddlevel value to be passed into translator + */ +uint32_t getChipLevel (TARGETING::Target* i_target) +{ + TARGETING::Target* l_chip = i_target; + + TARGETING::Target* l_parentChip = const_cast + (TARGETING::getParentChip(i_target)); + if( l_parentChip ) + { + l_chip = l_parentChip; + } + + TARGETING::ATTR_MODEL_type l_model = + l_chip->getAttr(); + TARGETING::ATTR_EC_type l_ec = + l_chip->getAttr(); + + // convert to scominfo types + uint32_t l_chipLevel = 0; + switch( l_model ) + { + case(TARGETING::MODEL_NIMBUS): + switch(l_ec) + { + case(0x10): + l_chipLevel = P9N_DD1_SI_MODE; + break; + case(0x20): + l_chipLevel = P9N_DD2_SI_MODE; + break; + + case(0x00): + // before ATTR_EC is set, default to newest level + l_chipLevel = P9N_DD2_SI_MODE; + break; + default: + TRACFCOMP( g_trac_scom, + "Unsupported Nimbus EC 0x%X", l_ec ); + assert(false,"Unsupported Nimbus EC"); + } + break; + case(TARGETING::MODEL_CUMULUS): + switch(l_ec) + { + case(0x10): + l_chipLevel = P9C_DD1_SI_MODE; + break; + case(0x20): + l_chipLevel = P9C_DD2_SI_MODE; + break; + + case(0x00): + // before ATTR_EC is set, default to newest level + l_chipLevel = P9C_DD2_SI_MODE; + break; + default: + TRACFCOMP( g_trac_scom, + "Unsupported Cumulus EC 0x%X", l_ec ); + assert(false,"Unsupported Cumulus EC"); + } + break; + default: + TRACFCOMP( g_trac_scom, + "Unsupported Chip Type %d", l_model ); + assert(false,"Unsupported Chip Type"); + } + + return l_chipLevel; +} + + } // end namespace //@TODO RTC: 139953 //Need to support centaur chip translations diff --git a/src/usr/scom/scomtrans.H b/src/usr/scom/scomtrans.H index 5b1d8e90b..f78249daf 100644 --- a/src/usr/scom/scomtrans.H +++ b/src/usr/scom/scomtrans.H @@ -89,6 +89,15 @@ errlHndl_t p9_translation (TARGETING::Target * &i_target, bool getChipUnit (TARGETING::TYPE i_type, p9ChipUnits_t &o_chipUnit); +/** + * @brief Computes the chip/ddlevel value to be passed into translator + * + * @param[in] i_target SCom target is passed in + * @return uint32_t Chip/ddlevel mode value for target, + * see p9_scominfo.H for values + */ +uint32_t getChipLevel (TARGETING::Target* i_target); + }; // End namespace -- cgit v1.2.1