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* Cumulus initfile update for OBUS & XBUS PLLsSoma BhanuTej2018-03-131-0/+18
| | | | | | | | | | | | | | | | Change-Id: Iea4f597ee6d58d8fc5d700bbc1273a69d77fc995 Original-Change-Id: I81e288c9160036bb3768c9172e860293f325a8d3 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41099 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55522 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* adjusted mem 2400 nest 1600 workaround and make dd1 onlyShelton Leung2018-03-131-0/+17
| | | | | | | | | | | | | | | | | | Change-Id: I23f74b4c525ac37460f5fb1a7b8fff16863ae314 Original-Change-Id: Iabf4b8a03eb2ae6c97ed2b6c96a0f6eed190fba6 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41128 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Dev-Ready: SHELTON LEUNG <sleung@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55521 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* P9 Cumulus InitCompiler supportis - Part 3Thi Tran2018-03-131-4/+5
| | | | | | | | | | | | | | | | | | | | | - Update *.mk files to support p9c chip ID - Workaround some spy issues p9c 10 engd issues - Fix bug to allow compilation without ENGD Change-Id: I9ba7057ddf5271a633bb87d8aa4df3a4b572d153 Original-Change-Id: Ie94b55c93081108668725d3ee9b88bd34eaa794f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40904 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Richard J. Knight <rjknight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55520 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* future proof EC feature attributes, add missing P9N DD2 initsJoe McGill2018-03-131-153/+130
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | redefine EC feature attributes, using inverse logic where required, to qualify inits specific to P9N DD1 where possible, to eliminate need for updates for future chips in plan attempt to remove usage of generic P9N_DD1_SPY_NAMES and P9N_DD2_SPY_NAMES attributes added to support initial P9NDD2 engineering data -- several spies were not being set as a result ----------------- initfile updates: ----------------- p9.cme.scan.initfile add HW391162, SCAN_SICR_TLBIE_QUIESCE feature attributes p9.core.common.scan.initfile remove fused core init, it was applying scan default for P9N DD1 and is not needed for P9N DD2+ given fuse controls p9.core.scan.initfile add CORE_P9NDD1 to qualify P9N DD1 specific register hierarchy and dial programming replace usage of P9N_DD1_SPY_NAMES, P9N_DD2_SPY_NAMES using CORE_P9NDD1 and inverse, to pick up initial pass at P9C DD1 inits p9.cxa.scom.initfile add CXA_P9NDD1_SPY_NAMES to qualify P9N DD1 specific register hierarchy p9.ddrphy.scom.initfile add DDRPHY_P9NDD1_SPY_NAMES to qualify P9N DD1 specific register hierarchy p9.dpll.scan.initfile remove POSTDD1N_DPLL_SETTINGS feature attribute, use DD1_DPLL_SETTINGS attribute and inverse to drive inits p9.l2.scan.initfile invert definition of OPTIMAL_LARX_STCX_PERF, HW409069 feature attributes p9.l3.scan.initfile p9.l3.scom.initifle remove OPTIMAL_LCO_SCOM, HW396230_SCOM feature attributes use HW386657, HW396230 attributes to drive inits p9.mca.scom.initfile add MCA_P9NDD1_ASYNC to differentiate asynchronous boundary crossing programming and dial name differences between P9N DD1, P9N DD2 p9.mmu.scan.initfile p9.mmu.scom.initfile invert definition of NMMU_DMT_DD2, NMMU_ISS734_DD2_1 feature attributes p9.ncu.scan.initfile p9.ncu.scom.initifle remove HW396230_SCOM, use HW396230 attribute to drive inits p9.npu.scom.initfile remove usage of P9N_DD1_SPY_NAMES, refactor CONFIG_ENABLE_PBUS specification to work for both P9NDD1, P9NDD2 ENGD p9.obus.scan.initfile remove EC qualification of OBUS FIR mask for simulation sample.ec.scan.initfile remove testcase requiring use of P9N_DD1_SPY_NAMES, properties of testcase are covered by other tests ----------------- HWP updates: ----------------- p9_xip_customize add customization of epsilon attributes for NMMU application p9_chiplet_scominit invert definition of P9_NDL_IOVALID feature attribute remove usage of P9N_DD1_SPY_NAMES p9_npu_scominit replace usage of P9N_DD1_SPY_NAMES with SETUP_BARS_NPU_DD1_ADDR p9_sbe_tracearray invert definition of CORE_TRACE_SCOMABLE feature attribute p9_sim_get_nia remove usage of P9N_DD1_SPY_NAMES, directly process CT/EC attributes (ok as this HWP is used for VBU sim only and not consumed by FW) Change-Id: I3269e9945cb9ef04dfd597e9c6f40d5ac3f01b0d Original-Change-Id: I63bfe8a4bfb8824b94e35a3688a6c69eecc1cf01 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40911 Reviewed-by: SHELTON LEUNG <sleung@us.ibm.com> Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55519 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* jgr17050500 Added Centaur and DMI IO SCOM initfilesJohn Rell2018-03-131-0/+18
| | | | | | | | | | | | | | | | Change-Id: I7e036d07bbb94cee5ecbef7d2a332a6aa5fd13b2 Original-Change-Id: I66e57795b5f9ca8c39ed244c7590a31e0c4cd79f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40154 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Richard J. Knight <rjknight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55518 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Update core inits for DD2Nick Klazynski2018-03-131-5/+314
| | | | | | | | | | | | | | | | | | | | Added update for new eng data Added missing spys to enable LSU trace Change-Id: If3d64ae9d97725dd8de478a542f49876854fbf37 Original-Change-Id: Iaed4992c45668c3da7cc692a3ccd02f6d1a5920a Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40380 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55517 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Updated memory DD1 vs DD2 attributeStephen Glancy2018-03-131-2/+2
| | | | | | | | | | | | | | | | | | Change-Id: If7395dc72ab91c14240037aa1f15d2e76e3bcd09 Original-Change-Id: Ie6d0f188a2ce94375535b0bf16c8ed1756558e5f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40632 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55516 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* L3 updates -- p9_build_smp, p9_fbc_utilsJoe McGill2018-03-131-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | p9_build_smp: constrain FFDC collection at 16 chips (current max size for P9 based systems) scrub node references, replace with group clarify X link requirements based on pump mode review and complete callouts p9_fbc_utils: add feature attribute to support pb_init sampling on NDD2+ replace locally defined bit constants with SCOM header file constants Change-Id: Icb2a2d4ab67a18537048ffef12203a1642efae06 Original-Change-Id: Ib1f71488ffd07580a647709d9227112f7d73384f CQ: HW328175 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40308 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: DHRUVARAJ SUBHASH CHANDRAN <dhruvaraj@in.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55515 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Adds DCD calibration control attributesStephen Glancy2018-03-131-0/+17
| | | | | | | | | | | | | | | | | | | Change-Id: Ifef1f631e84e2a46254968b844356e474ac0f8be Original-Change-Id: I2c3783eba2e5638e20136494ad897b420737566e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40178 Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55514 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Initfile updates for FBC DD2dchowe2018-03-131-0/+18
| | | | | | | | | | | | | | | | | | | Change-Id: I4b5705afd3ebcf52b91d03e2955f56a966a5c1bb Original-Change-Id: I18bf87b49f9bfba577bfc55fdf3cadc1fe09849f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39973 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: DANIEL C. HOWE <dchowe@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Dev-Ready: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55513 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* p9.int.scan.initfile -- init PSIHB to LSI modeJoe McGill2018-03-131-0/+17
| | | | | | | | | | | | | | | | Change-Id: Icd106a42e65f07193cb885c75d7b3e20acf4907b Original-Change-Id: I4d6811161d975b51063ad7e29e6b13b0d18750a3 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39593 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55512 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Update INT DD2 initfilesDavid Kauer2018-03-131-0/+17
| | | | | | | | | | | | | | | | | Change-Id: I301a6d2abe76e351bb7d129bbc5f05e347fc6d92 Original-Change-Id: Ia99d0dc53d5e18fdea9f430f0ec64ac40afe4eca Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40232 Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55511 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Updates for P9 NX DD2 initfilesChris Hanudel2018-03-131-54/+72
| | | | | | | | | | | | | | | | | Change-Id: Ie2ffe09ce1427326f9c0c7732625fb536c7e89ea Original-Change-Id: I811890df85ad59929c2ace02f9fe09b9fa3feb90 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38549 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55510 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Add DLL workaround and unit testsAndre Marin2018-03-131-54/+73
| | | | | | | | | | | | | | | | | | | Change-Id: I4f554e26cc96b30a8dbb132cbc56e1216069306d Original-Change-Id: I142ecd417abb92f4f8ec7d3748563b30359c486d Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39673 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Dev-Ready: ANDRE A. MARIN <aamarin@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55509 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* NMMU Nimbus dd2 scom/scan updates, updated commentsEmmanuel Sacristan2018-03-131-0/+82
| | | | | | | | | | | | | | | | | Change-Id: Ibfbc6652fba311f951ce8f43d607748891064df1 Original-Change-Id: I4b9296793fc8802f03bfebcb46446c8bc1a1d4e3 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39782 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55508 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Implementing Michael Floyds improvements.Michael Koch2018-03-131-4/+37
| | | | | | | | | | | | | | | | Change-Id: I98bc95095f71d9d795b37cfb0cfb5c37f959a0b4 Original-Change-Id: I719f5f2ab79755ec09f2420b6279569b0e05f3b2 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40148 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Anusha Reddy Rangareddygari <anusrang@in.ibm.com> Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55507 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Added DQS alignment workaroundStephen Glancy2018-03-131-0/+19
| | | | | | | | | | | | | | | | | | Change-Id: I25b48abdb4952b486ed2f4b1828800ad6570514c Original-Change-Id: Id03b903b964ae088bd427e333d4620a3412ea23c Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39508 Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55506 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* p9.xbus.pll.scan.initfile -- restore full frequency settings for Nimbus DD2+Joe McGill2018-03-131-0/+18
| | | | | | | | | | | | | | | | | Change-Id: I70370e6e39282167a5b9da970bf50c866f5861a8 Original-Change-Id: Ie19e0898f1b38087fc3fc95b9609c31152c7969a Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39866 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Megan P. Nguyen <pmegan@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55505 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* dd2 initsShelton Leung2018-03-131-34/+103
| | | | | | | | | | | | | | | | | | | Change-Id: I9c0bdb4656551a5747038f557d1bc3a9d943ca13 Original-Change-Id: Ice48f5752dcf18926b07fdd35bcc124c984ae2c3 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39732 Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55504 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* derate NVLINK frequency for Nimbus DD1Joe McGill2018-03-131-0/+17
| | | | | | | | | | | | | | | | | | | | limit to 20gbs Change-Id: I06c1cdf12a3516fe19574d0b45418c6412b444c4 Original-Change-Id: Ie348a42f0a0c305012dc91453d384b18459a0545 CQ: SW387041 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39616 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55503 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Performance updates for HW409069Luke Murray2018-03-131-0/+25
| | | | | | | | | | | | | | | | | | Change-Id: I31f39c48fa5584a9a857c4ce57ea6a654bb93de9 Original-Change-Id: I29c153d700f4fb8809f34cdf3ebaba4d6c4aff2b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39959 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: ALEXANDER M. TAFT <amtaft@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55502 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Change RD_CTR workaround val and update attr nameJacob Harvey2018-03-131-8/+8
| | | | | | | | | | | | | | | | | | | | Change-Id: I1502ba89751c47828203fcbb93188e6643c310ec Original-Change-Id: I00b2cf9cb54fdc4ec54b8f75ae1b9e687d2d4549 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39649 Reviewed-by: ANUWAT SAETOW <asaetow@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com> Dev-Ready: JACOB L. HARVEY <jlharvey@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55501 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* L3 initfile updatesAlex Taft2018-03-131-17/+18
| | | | | | | | | | | | | | | | | | | | | | 1) L3_CERRS_LRU_DECR_PROB_SEL_CFG should be left at default value and not altered 3) HW375255 should be applied to all systems since rejected by ccb 4) rddsp_demotion_init_lru_cnt_cfg performance chages Change-Id: I0a317d14b2c583837ebf4e5d7c977ea0d128985f Original-Change-Id: Ic36f360da342c8f98e940642b15111d0540ddfc6 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39577 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55500 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Adding HW401552 to cxa initfile to workaround clockgating bugJenny Huynh2018-03-131-0/+17
| | | | | | | | | | | | | | | | | | Change-Id: I644d47ae75e896e676c21b0215889f392118fd98 Original-Change-Id: I384afb523b07ed61e26c538a2477d1fb9eeaea6f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39474 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Oren Lev <orenle@il.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55499 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Updating HW363605 workaround to be applied to all chipsLuke Murray2018-03-131-17/+0
| | | | | | | | | | | | | | | | | | | MB was decommitted for all of P9 Change-Id: I2ef078eb3a9739491f1df680e2fd5ec99ff523e3 Original-Change-Id: I38850b1e0bdfe04290622fe1bf95e34ae9e9bf9a Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39448 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55498 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Disable cp_me from the L3 for Nimbus DD1 and DD2.0.Luke Murray2018-03-131-0/+17
| | | | | | | | | | | | | | | | | | | | | | By default the L3 only sends these when the addres is non-local. This is needed for the MCU to send early data. However MCU early data is broken in DD1 and DD2.0 and this eats up X-link bandwidth, so for DD1 and DD2.0 we're disabling cp_me from the L3. Change-Id: I02eae05d75265b6e25984e620e5ea3524b03b22e Original-Change-Id: I13a894f91434cc19f5f9502f54cc59bad9a0ae0f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39483 Reviewed-by: ALEXANDER M. TAFT <amtaft@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55497 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* INT scan initfile change to add workaround for HW408972Jenny Huynh2018-03-131-0/+18
| | | | | | | | | | | | | | | | | Change-Id: I942d7ce7785e556c58668dba76e4a7e810286afb Original-Change-Id: Ice09a8348e121a0cfbed458807486e46d2957813 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39390 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: DAVID M. KAUER <dmkauer@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55496 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* p9_setup_bars -- support DD2 NPU SCOM address changesCHRISTINA L. GRAVES2018-03-131-0/+18
| | | | | | | | | | | | | | | Change-Id: Ief409a8a4bae838c89888abbb17f44e430ce6c3c Original-Change-Id: I33afb42e7b29f58447aa430a07ca052c60f79cd4 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34965 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55495 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Updating optimal larx/stcx dials for performanceLuke Murray2018-03-131-0/+24
| | | | | | | | | | | | | | | | | Change-Id: I529aafd311b2ec3f6230ee17e3289ef4d104e9d2 Original-Change-Id: I4bb2fb68d1fe3383a435f0d938820cfa6d7db7eb Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39004 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: ALEXANDER M. TAFT <amtaft@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55494 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Added read ctr bad delay workaroundStephen Glancy2018-03-131-0/+17
| | | | | | | | | | | | | | | | | | | | | | | The workaround finds the median and moves delays below a specified percentage of this median to be the median value. Change-Id: I1c88ccb9bd2fb07477994bf8bad2249db9f3084a Original-Change-Id: I058c61a1e7734771ab31be3f48760030fbf945b5 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39178 Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com> Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55493 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* HW407123: Slow down xlink command rate for Nimbus DD1/2Jenny Huynh2018-03-131-0/+19
| | | | | | | | | | | | | | | | Change-Id: Ib4ef0db1bb8ac9540f0f510c871a438065ca59d2 Original-Change-Id: I5e1d5f6ff0b0139765d1dc30636cec30b91e37d6 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39132 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: DANIEL C. HOWE <dchowe@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55492 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Update filter pll settings as per HW407180Ben Gass2018-03-131-0/+18
| | | | | | | | | | | | | | | | | | | | | Nimbus dd2 and Cumulus use the same settings attribute indicates Nimbus dd1 settings. Change-Id: I42b389e50db1fd9addbf91725cf3e0f5fac81d3a Original-Change-Id: Ib54038a0e1389fe0ec812f9fefe14d55473c5c67 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38847 Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Ann C. Wu <annchen@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Brent Wieman <bwieman@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55491 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Fix for HW397129-set bit 52 in the ALTD_OPTION reg to keep MC fastpath enabledCHRISTINA L. GRAVES2018-03-131-0/+18
| | | | | | | | | | | | | | | Change-Id: Ic863c0dd3197dcd5a6aa648c666de504079e512e Original-Change-Id: Ifd5be240823ea2ba4fdb6950404b429e33363bd8 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36466 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55490 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Updating L3 LCO watermarks for HW406803Luke Murray2018-03-131-0/+17
| | | | | | | | | | | | | | | | | | | | | | In DD1 there is a bug in how the LCO home region is calculated so that the wrong bit44 vaule might be used. In the long run this works out to about half of the LCO home region being dropped. To help mitigate this, we're halfing watermarks for LCO's. Change-Id: I3a38b06bd4520a24b8634facaa732baa5e008ecd Original-Change-Id: I0d64d0e4a2bb72e1a413dc03612fc6e669b56be5 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38874 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: ALEXANDER M. TAFT <amtaft@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55489 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Adding good LCO settings to initfileLuke Murray2018-03-131-0/+41
| | | | | | | | | | | | | | | | | | | | Adding dials that give good roll out of the LCO's. Changing the count for the L3 LRU and turing on decrement mode with 1/4 prob. Change-Id: I495e7d13759fe3496f936e9b71c3d5686d2e4559 Original-Change-Id: Ib35475f5c1ce68d91a2cde44d8dcdc9a715f1361 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38380 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: ALEXANDER M. TAFT <amtaft@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55488 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* update DPLL and IVRM initsJoe McGill2018-03-131-0/+55
| | | | | | | | | | | | | | | | | | | | | | | create new EQ analog specific scan initfile shift application of eq_ana_func ring from cache_initf->cache_dpll_initf adjust DPLL FF slew rate add EC feature attributes for DD1 controls Change-Id: I03389ba59253aff06a142b2232f80c6838af3601 Original-Change-Id: I0000927e946f59e29f312dc9d5b5155676bb5d3c RTC: 170960 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37370 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55487 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* p9_sbe_chiplet_reset,p9_sbe_arrayinitAnusha Reddy Rangareddygari2018-03-131-0/+33
| | | | | | | | | | | | | | | | | | | | | | * assert SCAN_CLK_USE_EVEN=1 in OPCG_REG1 in cumulus chip MC chiplet * Cumulus only dropping MC chiplet fence during arrayinit Change-Id: I9071c43712c88fa1dcf6a3484410bcb7fc04c4ae Original-Change-Id: Id339b8707cb2caac62068bdea1c93465b43721e2 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38028 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55486 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* disable noise window for DD1 HW406577Shelton Leung2018-03-131-0/+17
| | | | | | | | | | | | | | | | | Change-Id: I1fdc5342507ca5bf47ded2b579549befbdc3c463 Original-Change-Id: Iff2cdae61e72f9ebdc020a730bc3d8ffd5b23118 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38313 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55485 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Attribute support of customization of Nimbus DD1 PCI reference clock speed.Thi Tran2018-03-131-2/+2
| | | | | | | | | | | | | | | | Change-Id: I9ddd9688087f38a27cdb9962f0791ce838e8d2b6 Original-Change-Id: I5bb1646868fca15aca744b311ab5d2bc5dd64739 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38297 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55484 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* HW406130: Reduce dma read requests from 16->8 in NX initsJenny Huynh2018-03-131-0/+18
| | | | | | | | | | | | | | | | | Change-Id: I530fb30145966aaea7de6751eb93e15f3ef3b32f Original-Change-Id: I194a441cda9076cddc5888dda20478677fa7a890 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38234 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55483 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Add risklevel for HW399624 due to perf penalty; Add HW405851Nick Klazynski2018-03-131-0/+17
| | | | | | | | | | | | | | | | | Change-Id: Icfb7c1cbbbeefef509a8182309055b7acc019ffa Original-Change-Id: Ib086218882ea5b8a32aa90ba55a4c1069ca461fc Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37999 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55482 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* p9_abist: Support for p9ndd2Markus Dobler2018-03-131-0/+17
| | | | | | | | | | | | | | | | | | | | | * sdis_n workaround also in dd2 * different bits for edram_done, sram_done in dd2 * option to stop RUNN (only works in dd2) Change-Id: If5167d80f4fad7b8261990b53a769f2d94465900 Original-Change-Id: I0bda7b431b87f59d1307329bcdffd0458818cb10 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37660 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph E. Dery <dery@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55481 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Add ec_abst ring to p9n.hw_imageThi Tran2018-03-131-0/+17
| | | | | | | | | | | | | | | | Change-Id: Iacd5a679b4597c7d2271a724eced3c5fdd55c960 Original-Change-Id: Ic6fc899956e0690f75224471917ff904aa03713e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37768 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55480 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* HW405413 : NCU sends data out of orderAlex Taft2018-03-131-0/+17
| | | | | | | | | | | | | | | | | | Serializes the data. Apply to DD1 only and risk_level 0 Change-Id: I8d354124fee8ed17132a85e1f517d66af4b85a5d Original-Change-Id: I4aa5d35b04afec2c20c7f6ea5d732210d1fe2f97 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37643 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55479 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Scrubbing needs to stay off for DD2, bug HW405443Juan Medina2018-03-131-1/+2
| | | | | | | | | | | | | | | | Change-Id: Ia179fd420eb0f189b70b67a217c816914b90d969 Original-Change-Id: I1421f90e1e6fe4b1e8cd73a9124daddade4026c8 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37666 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55478 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* PM: GPE timer fix (HW389045 - Update Shadow copy of TSEL)Greg Still2018-03-131-0/+17
| | | | | | | | | | | | | | | | | | | | - Tested in Cronus with U.H to pick up init from hw_image. - For Firmware, this change is needed in the SBE image!!!! Change-Id: I555f1633fc054ed80fa0ffbf60742ccac1c1515a Original-Change-Id: Ia8b087db972f6974d1ef6fbbda5dc4fb92e41693 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37508 Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Dev-Ready: Joachim Fenkes <fenkes@de.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55477 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Set NDL IOValids based on configured NV links.Ben Gass2018-03-131-0/+36
| | | | | | | | | | | | | | | | Change-Id: Ib6466ca54afa0ff54bb1fba651945fc6ff963e95 Original-Change-Id: I8dfc5410f4f4e6ec4b6fc6dc16b54b99da8f1641 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37375 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: DARREN J. DUFFY <darren@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55476 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* p9_start_cbs updatesAnusha Reddy Rangareddygari2018-03-131-0/+18
| | | | | | | | | | | | | | | | | | | | | | | Adding delay to wait for PibReset to complete Change-Id: I4faac50060bd4c53e7000cbb74559984cff03c0f Original-Change-Id: I79c9f591102c0114810348647c38d4b7fb762076 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37161 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Dev-Ready: Kahn C. Evans <kahnevan@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55475 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* enable prefetch drop for better MC fairnessShelton Leung2018-03-131-1/+18
| | | | | | | | | | | | | | | | Change-Id: I45f9a126102ff519866a794a76deef780a92a97b Original-Change-Id: I0fee2fe19b703e090ad2364a2a38dac31079b38f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37010 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55474 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Reducing rng pace rate from 2000 -> 300 for HW403701Jenny Huynh2018-03-131-0/+17
| | | | | | | | | | | | | | | | | Change-Id: I3c444f9e1a67cce76e06fbb9b6bf0a3b85104180 Original-Change-Id: I263cf15a6fa3a375590c813536f4b52ce915c4bd Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36919 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: CHRISTOPHER D. HANUDEL <chanudel@us.ibm.com> Dev-Ready: CHRISTOPHER D. HANUDEL <chanudel@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55473 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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