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* WAs for HW401811 HW402145 HW403465; DIS_MULTIPLE_TBLW on all modesNick Klazynski2018-03-131-2/+53
| | | | | | | | | | | | | | | | Change-Id: Ib3bb6737f27dee228a91a720a96e02a445314aff Original-Change-Id: I6a6803cc0f3571d41ae3e5fa501b89609b88d525 CQ: HW401811 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36063 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55463 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* amo cache disabled for dd1 for HW401780Shelton Leung2018-03-131-0/+17
| | | | | | | | | | | | | | | | | Change-Id: I611078d7d80cc600a88764f117a17b1298b521b1 Original-Change-Id: Iad3918c1d7e54b55ecc61f6d66181f0c05b1064a Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35839 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55462 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Adding HW363780 to NPU scom initfilesJenny Huynh2018-03-131-0/+18
| | | | | | | | | | | | | | | | | | | NPU fir bit can fire for any rcmd snoop that misses in the table lookup. Masking for nimbus dd1 only. Change-Id: Id1ad911a2b5057e5ac6a6fd0a612edc79d1e08bd Original-Change-Id: I0651b37279b0cee4ca5d383d83f0eb1079b75bd1 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35676 Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55461 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* workarounds for HW399919 HW400898 HW398269 HW398269 HW399765Nick Klazynski2018-03-131-0/+137
| | | | | | | | | | | | | | | | | Change-Id: I90340acbdc7ebf105a0ab86338ef7ddbcd2f57ca Original-Change-Id: Id84495c3b83d75e8fddd4833f04ec23614d223e2 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35406 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55460 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Added periodic cal fix - fixes bad delaysStephen Glancy2018-03-131-0/+18
| | | | | | | | | | | | | | | | | | Change-Id: I60d02448f6695aca0eb2c4e7a66eeebe62655acf Original-Change-Id: I8c55c2947dd85cc9ada45aaa9225ce641633f259 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35239 Reviewed-by: Brian R. Silver <bsilver@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com> Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55459 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* workaround for hw400932 atag corruptin in prespShelton Leung2018-03-131-0/+17
| | | | | | | | | | | | | | | | | Change-Id: I084b69293c5775524d113e81632d0580b5e90699 Original-Change-Id: I4a90407ed6fbf4bb9dbf64ee7e9c26b1e179784b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35287 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: DAVID M. KAUER <dmkauer@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55458 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* dd1 workaround for hw400075 coherency errorShelton Leung2018-03-131-0/+17
| | | | | | | | | | | | | | | | Change-Id: I13ea2522aff1b9a33a3a9d8b6c9eeeb62dced822 Original-Change-Id: I09ba40e8b92f7800a4843ff562cea3fbb75383c5 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35235 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com> Reviewed-by: Brian R. Silver <bsilver@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55457 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* VITAL cleaning for DD2Anusha Reddy Rangareddygari2018-03-131-19/+1
| | | | | | | | | | | | | | | | | | cq : HW399324 Change-Id: I14b9f49605d131b01c648536e4967bc236d82d60 Original-Change-Id: I4236b25b2587cb9705632dd55077c79e3d5cf246 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34827 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Abhishek Agarwal <abagarw8@in.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55456 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* p9.core.scan.initfile -- mask local error from CC in EC perv LFIRJoe McGill2018-03-131-0/+17
| | | | | | | | | | | | | | | Change-Id: Ic715c285a634a213e559236b526bb5936edecb4e Original-Change-Id: I1176cf9eba88a9f4f0b0309d15a44c45caf73ef9 CQ: HW401249 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35231 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55455 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* p9_sbe_tp_chiplet_init3 -- disable TP TOD hang pulseJoe McGill2018-03-131-0/+17
| | | | | | | | | | | | | | | Change-Id: I3522de333ddaac3bc4cd840fa695b6cd6681ecf5 Original-Change-Id: I838703170232b7ad39ae752f0fcde996f5bd577e CQ: HW401184 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35199 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55454 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Updating P9 L2 scan initfile to use attributesLuke Murray2018-03-131-0/+34
| | | | | | | | | | | | | | | | | | Change-Id: I6614698bb317604e138211dac24bff9301d22027 Original-Change-Id: I8aa808d2f0f3af8325af6900a0ec9fd5521183e5 RTC: 167767 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35194 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55453 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* FBC updates for HW383616, HW384245Joe McGill2018-03-131-0/+36
| | | | | | | | | | | | | | | | | | Change-Id: Ibeb804579c406e69a2046feba015981187d4e26f Original-Change-Id: I3b65925b1cadb6f4db5d64868f997ebf4ff7e625 CQ: HW383616 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34810 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: DANIEL C. HOWE <dchowe@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55452 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Adding skip group dials for cache when chip=groupLuke Murray2018-03-131-0/+41
| | | | | | | | | | | | | | | | | | | | | | The L2 dial is a scomable dial for DD1, but the NCU and L3 dials are not scan only for DD1. So the NCU and L3 have two dials one used in DD1 and one for after DD1. Change-Id: I89d566ba2291ebc8305b0711563800f4b2be5b62 Original-Change-Id: Ica63b417ae79b3b5a230c8034fd6f76b982df23b RTC: 167679 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34857 Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: ALEXANDER M. TAFT <amtaft@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55451 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Adding chip_ec_feature attributes for dd2 buildBen Gass2018-03-131-0/+1312
| | | | | | | | | | | | | | | | | | | | Resulting dd10 hw_image file matches the one generated from initfiles in master. Grub boots with resulting image and procedures. Change-Id: I7503e6031618d07684d8040f0b89b7e900f406ed Original-Change-Id: I2257448a7dcdb6be44da6196da847cca8ad4077d Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34736 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55450 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* add SS PLL settings to support 94 MHz PCI operationJoe McGill2018-03-131-0/+18
| | | | | | | | | | | | | | | | | support PCIE on DD1.x by lowering input refclock Change-Id: I553939495d62da9da7d8a68dd801196830c3dfa7 Original-Change-Id: Ic69f0b4cdcba9d667d08aa37aced6dbc4c156c98 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34389 Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55449 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* p9_getecid -- set PCIE DD1.0x workaround attributesJoe McGill2018-03-131-0/+34
| | | | | | | | | | | | | | | Change-Id: I0850f6ba81938ac4a68970197feca40e1cf607e1 Original-Change-Id: Ibef138e8d727c55ee564ffe2ee422fc79550162e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34676 Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55448 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Add MSS customization support from CRP0 Lx MVPDJoe McGill2018-03-131-35/+1
| | | | | | | | | | | | | | | | | | | | Keyword V0 offsets are the same as V1 Move bad-bits error processing to 1.03 Change-Id: I89d354b967133d0a2f3676e701f39ef03486d0be Original-Change-Id: I01e44c83f775b77e4ecc7afd7a5d92db524dfc98 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34073 Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55447 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Security control override disable support - p9_setup_sbe_configSoma BhanuTej2018-03-131-18/+0
| | | | | | | | | | | | | | | | Change-Id: If64e95c6fcb28822b60ca1e5954fe5eab09dc102 Original-Change-Id: Ia36d3ed31614976c25bef144c45396f577f037b7 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33401 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55446 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* p9.fbc.scan.initfile -- clock off MCSYNC staging latchesJoe McGill2018-03-131-0/+18
| | | | | | | | | | | | | | Change-Id: If9b88f0ee98e20fbf40b721db947af29ccdb0c8b Original-Change-Id: I7004f226a353e9075e8fe32e3bc157a58c36b4b5 CQ: HW397255 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33952 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55445 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* HW396520: DD1 workaround skip flushmode inhibit drop in cache hwpYue Du2018-03-131-0/+17
| | | | | | | | | | | | | | | | | Change-Id: I3f5ed727acc9bf5d2a554eb0eba2dcdb76faa388 Original-Change-Id: I6575ec51a94024708611678bee7af0cf7819b206 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33362 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com> Reviewed-by: ADAM S. HALE <ashale@us.ibm.com> Dev-Ready: ADAM S. HALE <ashale@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55444 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Add Memory Subsystem FIR supportBrian Silver2018-03-131-0/+17
| | | | | | | | | | | | | | | | | | | | | | | Add FIR.md to memory/docs Change some PHY workarounds, lab says hold off Add MC FIR to SBE code Change-Id: I1e69145f4d393d9185b93462ac42bbc9570983ad Original-Change-Id: I904079ab84d978637dd2b3e638c90d59395019fd Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33060 Dev-Ready: Brian R. Silver <bsilver@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55443 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Adding in defect HW395947,HW930007 to INT initfilesJenny Huynh2018-03-131-1/+72
| | | | | | | | | | | | | | | Change-Id: I2c3aab505b125e07d35071f824aff0ce1157bb0d Original-Change-Id: Iff8bed55ac363c8bd881fcc06f9cd3cd40261e15 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33369 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: DAVID M. KAUER <dmkauer@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55442 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Add EC workaround for PHY training bad bit processingBrian Silver2018-03-131-1/+20
| | | | | | | | | | | | | | | | | | | | Change-Id: I0860f6cee709b81c455d219b04c1466272cbb7de Original-Change-Id: Ia23b7bb80ae0875c869104b0557e7758d4df80a5 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33465 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Dev-Ready: Brian R. Silver <bsilver@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Brian R. Silver <bsilver@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55441 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* scan inits for lab workaround for DI bug HW392781Shelton Leung2018-03-131-0/+17
| | | | | | | | | | | | | | | Change-Id: I89be74beb51ca7ea4cd3a1fdf86b5d2727f30503 Original-Change-Id: Ia71c4d0933112c6804774b76a08ec5fbbe254833 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32780 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55440 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* p9_sbe_lpc_init fix with GPIO resetCHRISTINA L. GRAVES2018-03-131-0/+16
| | | | | | | | | | | | | | Change-Id: I408f12ed6fcf46ab42d700547e7a91a674968b5f Original-Change-Id: I019d7ba16b4e39b5cf140fe1461218736ce329f5 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32199 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55439 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Adding workaround for HW930007 and HW386013Jenny Huynh2018-03-131-0/+18
| | | | | | | | | | | | | | | | | Change-Id: Ia2904b70db3e247343cea6c9db65325d6368f675 Original-Change-Id: I934d63af496da2789ab69d857afe36cb1657175c Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31500 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: DANIEL C. HOWE <dchowe@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55438 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Istep4: Enable poll for DPLL lock in p9_hcd_cache_dpll_setupYue Du2018-03-131-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | changes in this commit: 1) enable dpll lock checking in non-sim envrionment 2) change FAPI_DBG lines on set/reset sdis_n ops as removing prints saying they are DD1 only workaround due to they are permenant steps now 3) add missing content of p9_hcd_core_dcc_skewadjust 4) add DD2 sram_enable support (NOOP for DD1) Change-Id: Ib03fa31f7ecc3eb2038a0342f89cb57db29d33b2 Original-Change-Id: I74fc3b05781e7cd13bb8c95b0dc7389029d7c5af Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31719 Reviewed-by: Joseph E. Dery <dery@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: CHRISTOPHER M. RIEDL <cmriedl@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55437 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Add EC feature levels to MSS workaroundsBrian Silver2018-03-131-12/+140
| | | | | | | | | | | | | | | | | Change-Id: I5a4c64e7a0ff61e4712a9efecab9291e29044170 Original-Change-Id: Iec6db88808f26353ce88f9038222db12f2d9b6c0 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32421 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55436 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* p9_psi_init -- parametrize link speed (half/full)Joe McGill2018-03-131-0/+18
| | | | | | | | | | | | | | | | | | | | Wrapper tested on zzfp033 Appears to correctly trigger half speed mode from FSP tool feedback $ cat /sys/devices/psi_link0/clock FSP-2, PSI(0) CLK overwrite: 1 Speed: 166 MHz Change-Id: Id03e7fd54a3eff8037ac677399472dbd8a89d1a1 Original-Change-Id: I45997c30e71457ceedfcba70550f0e6d98584a1e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31497 Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55435 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* PPM reg collision (HW389511) work-around: Special Wake-upChristopher Riedl2018-03-131-0/+17
| | | | | | | | | | | | | | | | | | | | - fixed screwed-up/duplicate commits - addressed code review comments and implemented FAPI_ASSERT conditions for the error case(s) Change-Id: Ie0ff20f2a9a5ed2d6cf9dc9ce797a14b0280a8f0 Original-Change-Id: I706b3247f0f9c3ea241ae2841fbce456577c78b6 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31379 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55434 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* p9.fbc.scan.initfile -- create initfile, add workaround for HW376651Joe McGill2018-03-131-0/+18
| | | | | | | | | | | | | | | | | Change-Id: I8203ea499195a1231d022233ef1f1a115a2b29c7 Original-Change-Id: Iaccfdf902d179819549f46ddee65631873fa023e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31309 Reviewed-by: DANIEL C. HOWE <dchowe@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55433 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* HW388878 VCS workaroundJoe McGill2018-03-131-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In pre-poweron HWP, Reset ROOT CTRL and PERV CTRL regs to cold IPL state Tested with poweron flow which: drops all rails (preserving Vstandby) executes pre-poweron HWP to reset cfam region regs enables rails (excluding VCS) executes cfam pop start sequence enables VCS rail Add defect number to feature attribute, used in all consumer HWPs Change-Id: I4575cd9de5bf0f6c933b8695de3f77e866156bb0 Original-Change-Id: I5bf5d61033bdca97527c8b499995eb6920ac1122 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31101 Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55432 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Cache HWP: DD1 VCS WorkaroundYue Du2018-03-131-0/+18
| | | | | | | | | | | | | | | | Change-Id: If85a64ccd6de8872578e17a5669633ceb688a281 Original-Change-Id: I9634a767878904f810cb1e6a0767ba4bbad241cb Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30827 Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55431 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Change chip to unsecure always for DD1 chipsSoma BhanuTej2018-03-131-0/+18
| | | | | | | | | | | | | | | | | Change-Id: Ic3380115d4beb6aa0ddd584cbeac53f561330021 Original-Change-Id: I73e2aace7ad9a56bfd528b4b2d82741148df971f RTC:158131 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30952 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55430 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* DD2 updates:p9_sbe_arrayinit,p9_sbe_tp_arrayinitAnusha Reddy Rangareddygari2018-03-131-19/+1
| | | | | | | | | | | | | | | | | | | | | set/reset of dis_n are permanent steps CQ : HW389256 Change-Id: I86d54da49c750553feccf1cb4bfe14d024dfb24c Original-Change-Id: I70022293b7d375f94166a90127c8980038cd08e1 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30872 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: Tobias Webel <webel@de.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55429 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Procedures modified for DD1 changesSunil.Kumar2018-03-131-0/+17
| | | | | | | | | | | | | | | | Change-Id: I17510d3430f17ac782e0a23df7d8a887025437cf Original-Change-Id: Iaff301338637dac67457330698fa85383012186d Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27973 Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55428 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Ec_level attribute support for DD1 attributesAnusha Reddy Rangareddygari2018-03-131-0/+73
| | | | | | | | | | | | | | | | | --Fixig hb_temp_defaults.xml Change-Id: Ib0c5a588333e4273e10b36f1d0bde3c271797e6a Original-Change-Id: Iab140154483b10bd05a6dba092dad25f64eae742 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26450 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Andrew J. Geissler <andrewg@us.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55427 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Add p9_proc_gettracearray procedureJoachim Fenkes2018-03-131-1/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Generic procedure to dump a trace array. The API is similar to the P8 procedure, but the procedure takes trace _bus_ IDs as opposed to trace _array_ IDs and uses these to check the trace array's primary trace MUXes prior to dumping. There is also a flag to skip this check if you want to dump a specific trace array no matter which bus is muxed into it. The FAPI2 target supplied must match the trace array; most will just need a TARGET_TYPE_PROC_CHIP target, but some are targeted at OBUS, MCBIST, EX or CORE granularity. There's an inline function proc_gettracearray_target_type() that will help determine the target type. Change-Id: Ied7602b05a7441e4d2610b96ea77026d7a40b3c7 Original-Change-Id: I093cd03bc90fbe93ed8fff3d18cd0676359fa5d1 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22847 Dev-Ready: Joachim Fenkes <fenkes@de.ibm.com> Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55426 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Procedure crashes when trying to query an EC featureRichard J. Knight2018-03-131-0/+76
| | | | | | | | | | | | | | | | | | | | | | -Updated queryEcFeature to have two parts, base attribute reading is now in a library, while feature checking logic is now in small individual inline functions. Change-Id: Ie4c0f7d088624d4e444457fd795bed1ce2ba95d1 Original-Change-Id: I4c3685d6a85946297af31f7f3da4d918bca88039 RTC:151184 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23025 Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55425 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Remirror chip_ec_attributes.xmlDan Crowell2018-03-132-7150/+4
| | | | | | | | Change-Id: I15738ac513ee440514698593dab0096999a06f32 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55424 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Only call PNOR::init() on systems with BMCMatt Derksen2018-03-121-9/+14
| | | | | | | | | | | | | Code to fix SW412798 forgot to check for non-fsp systems. FSP systems will return an error. 0 size FIRDATA section. Change-Id: Ic2c2c49707d49b29cc38358ef6ab9dd372e8ffab Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55373 Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> CI-Ready: William G. Hoffa <wghoffa@us.ibm.com> Tested-by: William G. Hoffa <wghoffa@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
* Check the Section Headers in Non-Secure ModeIlya Smirnov2018-03-126-39/+100
| | | | | | | | | | | | | | | | | | | | | When a PNOR section without a header is flashed onto a system that doesn't have SECUREBOOT compiled in, no header checks are performed, but the code still acts as if the header is present, and so the virtual address of the section is set to point past the secure header, which is 0x1000 into the section image, which causes all kinds of issues. This change adds logic to check the headers even when Secure Boot features are compiled out. Change-Id: Ieece371014192f160273939a35cb175aef0ddb25 Resolves: #126 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54831 Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* No longer include BAR attributes in ServerWiz2 exportDan Crowell2018-03-121-0/+14
| | | | | | | | | | | | | | | | | | All of the BAR (Base Address Register) attributes are set based on an architected memory map. There is no reason to allow the MRW to modify these values. Change-Id: Ib4a8211a2251acfb66f786025ce7b3cd002d8331 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53863 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-by: Corey V. Swenson <cswenson@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
* Wait for responses from all nodes for IPC_POPULATE_ATTRIBUTES msgRichard J. Knight2018-03-121-6/+10
| | | | | | | | | | | | | | | | | | | -In the message handling for IPC_POPULATE_ATTRIBUTES the master node should wait for a response from all messages, the current code only waits for a single response. The change in this commit adds a loop to capture a response from each message sent. Change-Id: Iec3d3f666a3f00e01b850a822674d3f479f8bc89 RTC:189354 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55249 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Richard Ward <rward15@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Secure Boot: Dynamically set TPM I2C master path in MRW parserNick Bofferding2018-03-121-1/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | Historically the TPM target as described in the MRW passes directly through to the Hostboot targeting model without modification (other than filtering out unwanted attributes). This approach does not work in multi-TPM or multi-node systems since the TPM object's I2C master path gets cloned within and across nodes. Instead, for multi-node systems, the MRW parser must now walk the I2C bus connections between each TPM and the chip driving it, and dynamically compute/set the TPM's I2C master path. This behavior only activates for multi-TPM systems due to limitations in other workbooks, as in these cases, the pre-existing behavior sufficies. Change-Id: I5845760a390841d083dc0bbe633bc19a90ab23e6 RTC: 184515 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55240 CI-Ready: Nicholas E. Bofferding <bofferdn@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Santosh S. Puranik <santosh.puranik@in.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: ILYA SMIRNOV <ismirno@us.ibm.com> Reviewed-by: Marshall J. Wilks <mjwilks@us.ibm.com> Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
* Created individual update flags for both SEEPROM 0 and SEEPROM 1Roland Veloz2018-03-122-8/+20
| | | | | | | | | | | | | | | | | | I created individual update flags for both SEEPROM 0 and SEEPROM 1 to better target which seeprom to update. Now SEEPROM 0 or SEEPROM 1 or both can be singled out for update(s). Change-Id: I91f1b66f6a1f2e42d37173fb9e21f87e440d3a21 RTC: 189218 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55173 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
* Secure Boot: Check integrity of dynamically sized secure header copiesNick Bofferding2018-03-123-39/+141
| | | | | | | | | | | | | | | | | | | | When reading a secure header, the container header object can overrun a buffer when number of ECIDs or software keys specified is greater than the supported amount. This change implements hard enforcement to ensure that this is no longer possible. Change-Id: Ife9194763f858b37e2de6f12fa01d74da1145df3 CQ: SW419735 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55088 CI-Ready: Nicholas E. Bofferding <bofferdn@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: ILYA SMIRNOV <ismirno@us.ibm.com> Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com> Reviewed-by: Marshall J. Wilks <mjwilks@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
* Do not elevate severity of reconfig error logDan Crowell2018-03-121-4/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The code as currently written will elevate the severity of any log that is used to terminate the hostboot ipl. In most cases this is the correct behavior as we always want a visible log. However, there are cases where hostboot terminates for the sole purpose of triggering a reconfig loop via the FSP in order to recover from a recoverable hardware issue. In this case the log shouldn't be visible since we don't want the customer to take any actions. The fix is to add a little bit of logic to differentiate these two scenarios to control the severity setting. Change-Id: I7253aec8c28a40c5cdebf4933ceccbecd119b9f4 CQ: SW420495 Backport: yes Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55379 CI-Ready: Nicholas E. Bofferding <bofferdn@us.ibm.com> CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com> Reviewed-by: Marshall J. Wilks <mjwilks@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
* Fixed MNFG Attribute handing for TCE CorrectionsMatthew Hickman2018-03-111-3/+4
| | | | | | | | | | | | | | | | | | Change-Id: I125bfbcb025b24a771d8c899d9045677878e064f CQ: SW419525 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55198 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55208 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Fix EID range for HBRT logsDan Crowell2018-03-091-0/+1
| | | | | | | | | | | | | | Add back in the lost 0x89 subsystem specifier to the HBRT error logs. Change-Id: Idf9a5a90e79137df3745e5a3d387255e5c87f715 CQ: SW420482 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55364 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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