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* Add perf inits: HW418850,HW418789; Add clockgate issue HW418738Nick Klazynski2018-03-131-0/+72
| | | | | | | | | | | | | | Change-Id: I9c3c1a8b591c8fd2996d2b22d31c01b2863d0089 Original-Change-Id: I4ecc57a12091a5c309bf33584e38dd6d247054a9 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44802 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55563 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* resolve Zeppelin DMI channel framelock issuesJoe McGill2018-03-131-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | p9_sbe_chiplet_reset p9c_mc_scom resolve HW CQ 418671 set MC CPLT_CONF1 FASTX2 ratio controls in p9_sbe_chiplet_reset need to set prior to MC chiplet clock start for proper functional operation remove from initfile p9_cen_framelock resolve HW CQ 418901 analyze captured FRTL value along with FRTL counter overflow error FIR centaur.mcs.scan.initfile cen_scominits enable MBI trace array prior to framelock, to make usable for future debug Update p9c.mc.initfile to include fix for ZCAL to help with conflicts - bgass Change-Id: I94862c5f4122e5ccafb15ac3ab9e519ea523a27e Original-Change-Id: I7897d41250b9c113adf22fe40a8ca5971bca2a6f CQ: HW418671 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44708 Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: LENNARD G. STREAT <lstreat@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55562 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Mistakenly pulled workaround for HW410212 - readd for CDD1.0Nick Klazynski2018-03-131-1/+8
| | | | | | | | | | | | | Change-Id: I374c8e72582d028a4612b449696d9040f402025d Original-Change-Id: If2d1fa278b8d614b995a07ff3da1a81d508f692c Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44748 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55561 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Reverting chickenswitches for issues fixed in Cumulus DD1.0Nick Klazynski2018-03-131-58/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Differences: HW407282 - No dial - spreadsheet says to remove? HW407065 - Removed - spreadsheet says nothing to remove? HW408512 - No dial HW408891 - Removed HW407065 - Removed HW408628 - Removed HW408917 - Removed HW409270 - Removed HW409194 - Removed HW409355 - No dial HW410212 - Removed - (HW417242) HW411571 - No dial - spreadsheet says to remove? Change-Id: I9ae0ebb66091ee771315e0f606d2981989e4d71c Original-Change-Id: I460b214240498738c0f63a1cad055d1a57cdd71f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44600 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55560 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Update core initfiles for Cumulus DD1.0Nick Klazynski2018-03-131-50/+414
| | | | | | | | | | | | | | Change-Id: I9522c91b9c94e5db71f69cd71b61b0f75a8e94d0 Original-Change-Id: I5fddc89dbb3b1759c0690c562430208429b08b4d Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44310 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55559 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Modified gen_accessors script for greater supportAndre Marin2018-03-131-0/+18
| | | | | | | | | | | | | | | | | | | | | | Added support for PROC TARGET, only creates accessors for attributes that have the mssAccessorName xml tag, added support for other non-mss attrs that don't have [port][dimm] indexes and that have target types other than MCS, MCBIST, and SYSTEM Change-Id: I4f667acd9de455a779cded183aa357b52dcf1efb Original-Change-Id: I6c76f8e7bbc0be1dade3f77f78d3371d16b609b2 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44255 Reviewed-by: Louis Stermole <stermole@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55558 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Use DD1 SW reset for XIVE unit until we get HW reset working in DD2crgeddes2018-03-131-0/+18
| | | | | | | | | | | | | | | | | | | | | This is a temporary workaround until we get the HW reset working. Currently we are having issues with the VSD tables not getting cleared correctly when Hostboot tries to initialize interrupts Change-Id: Id503cdc2c6192aaeb0ea6c25257fa04136dbc6ca Original-Change-Id: I313cb9cbba63cb0598b663c9792acf798b1c8766 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43632 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55557 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* p9.int.scom.initfile -- mask SUE FIR for Nimbus DD2Joe McGill2018-03-131-0/+17
| | | | | | | | | | | | | | | | | | Change-Id: I13ac31203e68d1759214b55f19fb7114597e534e Original-Change-Id: I8c921e4d6adf441daa6892e56fc1208081a6fb48 CQ: HW411637 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43637 Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: DAVID M. KAUER <dmkauer@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55556 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Add additional dials to risklevelNick Klazynski2018-03-131-0/+17
| | | | | | | | | | | | | | | | | Change-Id: I4a63f3333b7aaeffa023ee066ff1be61f4b98371 Original-Change-Id: I94463fc5b28d4912439431ca89aa622661ed4034 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43635 Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55555 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Remove reset_dll from scominit, enable delay line tap pointsAndre Marin2018-03-131-3/+20
| | | | | | | | | | | | | | | | | | | | | | | | reset_dll API was found to be redundant to what already exists in the initfile per John Bialas. Removed if from scominit. Also included initfile changes that John made by enabling delay line tap points Change-Id: I7f165089ee7848f0b93cb4e7d4e25b0e7d609c79 Original-Change-Id: Ide517e8dced5176d508dcb352e041e09da206a09 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43018 Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55554 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* p9.npu.scom.initfile -- FIR updates to align with RAS XML documentationJoe McGill2018-03-131-0/+35
| | | | | | | | | | | | | | | | | | | | create feature attribute to qualify FIR2 inits update FIR2 XML,inits based on current review feedback Change-Id: I32ea02b4facd6f3e9b20dcd549660157f303eca2 Original-Change-Id: I8a1a8a92e4f4ee24b308f0bb731a953f098edc72 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42910 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55553 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* TP, Nest FIR updates -- DD2 updates to match RAS XMLJoe McGill2018-03-131-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TP Pervasive LFIR - mark bit 21 recoverable to match XML specification - add Nimbus-only workaround for XBUS PLL lock reporting - adjust MEM PLL reset,setup routines to avoid generating spurious attention from MEM PLL FBC IOE TL FIR - mask bits 9,12,15 to match XML specification - mark bits 56..58 checkstop to match XML specification FBC IOO DL FIR - mask bits 56..59, 62..63 to match XML specification - mark bits 60..61 recoverable to match XML specification IO OBUS FIR - mark bit 2 recoverable to match XML specification CXA FIR - update initfile to handle change in number of implemented bits from Nimbus DD1 to DD2 NX CQ FIR - mark bits 6,16,20..21,23..24,28,39 checkstop to match XML specification - mark bit 11 recoverable to match XML specification changes Change-Id: Ic2bdf913ef98b6ad1ae6b94fe1e8a2ae8dacad70 Original-Change-Id: Ic954b2281d1d86ad91e7cd4952923af8c0fa0d8b CQ: HW415692 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42905 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55552 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* GPTR/Overlays stage-2 supportSumit Kumar2018-03-131-2/+2
| | | | | | | | | | | | | | | | | | | | | | | -Updated ringClass to include Gptr for Nest/EQ/EX/EC to support CME/SGPE. - Bug fixes: - big endian to local host endian conversion - now also processing Gptr rings in RT_CME/SGPE sysPhases - improved error checking, error capturing and trace outs Change-Id: I79a9220fe715ad021a2502eb17f2b17a047dadff Original-Change-Id: Idfc19bdf1b7187d6f75c459f7ddbeda80ccfec28 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43080 Reviewed-by: Claus M. Olsen <cmolsen@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55551 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* p9_sbe_tracearray: Nimbus DD2 updatesJoachim Fenkes2018-03-131-0/+18
| | | | | | | | | | | | | | | | | | | | Adapt "trace still running" check for DD2, and make use of the new "hold trace_run off" functionality in the process. Backwards compatible with DD1. Change-Id: If6127007c0a598506193a5fe8201c0ba426a0097 Original-Change-Id: Iab06937700039a5bb9c14acfe4942e4ae1c29352 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41575 Dev-Ready: Joachim Fenkes <fenkes@de.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55550 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Create dmi.pll.scan.initfileBen Gass2018-03-131-0/+17
| | | | | | | | | | | | | | | | | | | | | Support sync and async mode for Cumulus MC Default buckets are 1. Change-Id: I92036cfaee8bf52b8ad37560084b11f86fbd40d5 Original-Change-Id: I62d0221abf7f93030cb8c0200a456609ab4dfe04 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40326 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55549 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Add WA for HW415988Nick Klazynski2018-03-131-0/+19
| | | | | | | | | | | | | | | Change-Id: I2d948c37f3533ffab330f6cdbc57ce67515f9d56 Original-Change-Id: Ice266e03ce57248c4e45ba49302353247c47ede7 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43068 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55548 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* HW414700 checkstop on UEs and disable core ECC counterLuke C. Murray2018-03-131-0/+18
| | | | | | | | | | | | | | | | | | | Core ECP.PC.FIR.THRESHOLD_RESET = 0b00 to disable CXA, L2, L3, NMMU, NX, VAS, FBC, MC FIR changes to checkstop on UE at source Change-Id: I470fb3d6708bff20b8033b78a7ee5cdbe624ca7a Original-Change-Id: I4400acb7d3ec68cced49adb5a77fec7bd8356d40 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42887 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55547 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* xip_customize: GPTR/overlays stage 1 supportClaus Michael Olsen2018-03-131-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updated to poll Nimbus DD level and whether there's support for overlays in the XIP interface. Further, updated to add three extra args in xip_customize API, two of which are to support a third ring work buffer for the overlays handling. This has necessitated making changes to hcode_image_build (HIB) API as well. Note that the calling codes of xip_customize and HIB need to be updated to supply the additional args in their APIs. Note that this code stage 1 will work for Nimbus DD2 with Gptr rings in Mvpd, and no Gptr rings in the HW image. It will, however, not work if there's content in .overlays or if there's Gptr rings already in the .rings section. Thus, the stage 1 code here will work with a DD2 image (i.e., that does NOT have Gptr rings in .rings in HW image) as long as noone has put any real Gptr initfiles in for processing (which would result in ring content in .overlays). We must ensure that the stage 2 code of xip_customize gets merged on the HB side to enable processing of .overlays content before we actually add any Gptr initfiles for the .overlays section into EKB. Change-Id: I1b7b040513f161be6bd8b2c594be1edb254a7cd5 Original-Change-Id: I3d6ab8a9add239c92819613dcae21ef5faf0a1c5 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40591 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sumit Kumar <sumit_kumar@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55546 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Add WA for HW415236Nick Klazynski2018-03-131-0/+17
| | | | | | | | | | | | | | | Change-Id: If91b9228d112581102f5d3d7ae66c17742dc96e2 Original-Change-Id: I87d525df67248d54a91283429f985e61a43fade2 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42991 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55545 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Add Workarounds for HW415114 HW415013 HW413853 HW414384Nick Klazynski2018-03-131-0/+119
| | | | | | | | | | | | | | | | | | - Add HW415114 HW414370 HW414597 HW415480 Change-Id: If35a8d364d600dce8b2032ea4c259bfe06c903ba Original-Change-Id: I170e1dcbe4f3535e078d28791ba7cd84974ec6d0 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42773 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55544 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Update FBC cd_hp initfile to reference serial mode spys directlydchowe2018-03-131-0/+18
| | | | | | | | | | | | | | | | | Change-Id: I6aeda66916e31f84d0da913e2c961c094a95efbb Original-Change-Id: I7672defe7313413867199a9c486faf3d04e9ebd3 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42857 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55543 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* PSTATE_PARAMETER_BLOCK structure alignment and error handlingPrasad Bg Ranganath2018-03-131-0/+17
| | | | | | | | | | | | | | | | | | - Add VDM EC attribute to generally disable VDMs on Nimbus DD1 Change-Id: Ie9abb25033c514456cf93fa9fc23c873aa2553bc Original-Change-Id: I7743bbff9c8f975074068d760373b8b9b8294d32 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42714 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Adam S. Hale <adam.samuel.hale@ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55542 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Disabling LVext for all P9 partsLuke C. Murray2018-03-131-18/+0
| | | | | | | | | | | | | | | | | | | LVext is removed in P10, so it was decided to remove LVext for all of P9 rather than add and then take back. Change-Id: I3a0acfc4ed65a50205a11c62d935c93613c9f6f2 Original-Change-Id: I51d76174de5eaa91f442e59083afa74b3bd81d37 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42823 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55541 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* p9.npu.scom.initfile -- Nimbus DD2 updatesJoe McGill2018-03-131-18/+0
| | | | | | | | | | | | | | | | | | | | mask NPU.IDIAL_SM_MASK_NLGX_0 for all ECs set NPU.CONFIG_DISABLE_VG_NOT_SYS for all ECs Change-Id: Ia6a3b753f4aba83446361d3573f73c3d241df85a Original-Change-Id: Ief91a75430932f01d643cadee60f3d707e1ea048 CQ: HW413726 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42691 Reviewed-by: RYAN BLACK <rblack@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55540 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Cumulus proc updatesAnusha Reddy Rangareddygari2018-03-131-2/+3
| | | | | | | | | | | | | | | | | | for osc switch settings Change-Id: I3cd8f2c5be26e93f86dd0909e0e218afb31f9dae Original-Change-Id: I9e762d2c4b552e84a3a2cc48ec0d9d75732b07cf Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41676 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55539 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* p9.pci.scan.initfile -- initial releaseJoe McGill2018-03-131-0/+16
| | | | | | | | | | | | | | | | | Change-Id: I9cd80b7ae61aa6bf0da05ddb9c065281b55c1690 Original-Change-Id: Ibcb861641ff420ecdb763fde2db4577037b64f03 CQ: HW399276 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42774 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Dev-Ready: Ricardo Mata <ricmata@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55538 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* DD2 updated scan overrides, Cumulus DD1 initfile updatesdchowe2018-03-131-0/+25
| | | | | | | | | | | | | | | | | | Change-Id: Ic05e0d6e494e56a94a761e085662d36ee525c866 Original-Change-Id: I1b66fdf7786a2358b304b6b3d5bbc6b92d06e4e1 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42380 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: DANIEL C. HOWE <dchowe@us.ibm.com> Dev-Ready: Brent Wieman <bwieman@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55537 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Add WAs for HW413799 HW413853 HW413917 HW414249 HW414375 HW414871 HW414829Nick Klazynski2018-03-131-0/+119
| | | | | | | | | | | | | | | | | - Commented out HW413853 until we get risk level working for DD2 Change-Id: I7c581f4714f64ca1e489fdbf2bd308fef4b36e3d Original-Change-Id: Ia07c08032e75fd295b2275e1785cbe47db381a64 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42515 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55536 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Adding HW414702 workaround to INT scan initfilesJenny Huynh2018-03-131-0/+18
| | | | | | | | | | | | | | | | | Change-Id: I4ee7ee74a5648d0d117c2438ed661e93fd3061a0 Original-Change-Id: I107ae828c1a7c4fc56a4ec520f05fff00560adb5 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42402 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: DAVID M. KAUER <dmkauer@us.ibm.com> Reviewed-by: Kahn C. Evans <kahnevan@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55535 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* PCIe updates for Nimbus DD2 GEN4 operationJoe McGill2018-03-131-0/+18
| | | | | | | | | | | | | | | | | | | | adjust REFISRC, REFISINK, VBGENDOC in PCIE PLL inits for all ECs set EDMOD in RX VGA Control Register 1 for DD2 only Change-Id: I2944edbba2ac7121f0ee0e57b3667d0de3215506 Original-Change-Id: Ib10b02fb49dbf7ccf8dcad2ada5ac463a927d4c7 CQ: HW414759 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42423 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Ricardo Mata <ricmata@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55534 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* p9.core.scan.initfile -- set disable 241 for Nimbus DD2Joe McGill2018-03-131-3/+3
| | | | | | | | | | | | | | | | | | Change-Id: I2c797802fcf06402f2754249cbed6e20276f8ccd Original-Change-Id: Icb27247b318b612664c25f1121a8f80a5feb014c CQ: HW413718 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42425 Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55533 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Fixed DLL workarounds to always runStephen Glancy2018-03-131-17/+0
| | | | | | | | | | | | | | | | | | | | | | | DLL workarounds will not be fixed in hardware, in the foreseeable future. As such, always run the workarounds. Change-Id: I735a6c94222a931a7395d880ab11fcb644bfcaf2 Original-Change-Id: Iaa48b1b976908fdbb8af1eb8d518147fabc8cdce Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41998 Reviewed-by: LUCAS W. MULKEY <lwmulkey@us.ibm.com> Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55532 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Workarounds for HW407385 HW408629 HW410389 HW408901Nick Klazynski2018-03-131-0/+68
| | | | | | | | | | | | | | | Change-Id: Ia65dbc4926a058dc58faa1c6e63f069b1b688ec0 Original-Change-Id: Ibede50b260275ce35703a411d6f622e444b1ed4a Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41890 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55531 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* L3 Initfile: Qualify divide_minor settingAlex Taft2018-03-131-0/+17
| | | | | | | | | | | | | | | | | | | | L3_REF_TIMER_DIVIDE_MINOR needs to be left at default value of Divide by 10 for DD1.X, DD2.0 due to bug Change-Id: I968835bd53776a2d51d263fa2d7da4a36129849f Original-Change-Id: I9bfbf243ecf854c2375e852f60d0bcb47812fe87 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41893 Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55530 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* dd2 phy scom initsShelton Leung2018-03-131-0/+17
| | | | | | | | | | | | | | | | | | | Change-Id: Ied68fb7343087fbfe3edd639ece47417167981f1 Original-Change-Id: Icb3b25a75b71e40135237c784ac584ec54516d2e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41849 Dev-Ready: SHELTON LEUNG <sleung@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Kahn C. Evans <kahnevan@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55529 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Use obus p9ndd1 spy name attribute for obus initfileBen Gass2018-03-131-0/+17
| | | | | | | | | | | | | | | | | Change-Id: I014e8616e5151cf4cb5cde51841a9f663e92ed8d Original-Change-Id: I0b51976c6ee4094825128a30dca042e37ccfe3e3 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41880 Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Richard J. Knight <rjknight@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55528 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Add core workaround for HW407136Nick Klazynski2018-03-131-17/+17
| | | | | | | | | | | | | | | | | | | Remove ATTR for HW396388; EN_ATTN is needed for all chips Mask PC_OTHER_CORE_CHIPLET_SYS_XSTOP_ERROR for SW390012 Change-Id: I4f5ad10bcaedbffd55dc3a6cd3ae5c4e15b2ad11 Original-Change-Id: I70280ca7dfdd22ee88780c8cf76444283d1a4213 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41646 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55527 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Disable mem clk stop when in STR for DD2.* onlyAndre Marin2018-03-131-0/+17
| | | | | | | | | | | | | | | | | Change-Id: I9ba4b4cb4c43b7860b5be2930db1f6b5f90e3a74 Original-Change-Id: Ieeea636a6f0d62344f72d339a52c4a1b862fa258 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41459 Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Reviewed-by: Michael D. Pardeik <pardeik@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55526 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* L3 update -- p9_pcie_configJoe McGill2018-03-131-0/+17
| | | | | | | | | | | | | | | | | | | | | update owner comments address remaining todo items define constants to replace hardcoded bit definitions cleanup trace messages Change-Id: I8885f82aae43f6ce627e16e869788ec5a4dd8e12 Original-Change-Id: Ibc075046d4494d3ec5bf85780ee58c919c6b68a2 CQ: HW363246 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41116 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55525 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* PM: refine enablement attributes for advanced functions (VDM,RESCLK,WOF,IVRM)Greg Still2018-03-131-2/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Move to a "disable feature" attribute paradigm for SYSTEM control - Add consistent system enablement (eg Cronus, MRW) control attributes - Added HWP attributes to allow p9_pstate_parameter_block to indicate validation status to p9_hcode_image_build for Hcode header updates - Mark attributes as deprecated for future removal - Added HB system defaults to auto enable RESCLK, VDM and WOF. IVRM is disabled. - RESCLK only has override attributes so will enable function once code that looks the attributes is in a driver - VDM enablement forces the need for #W to be there and valid. Valid will be if #W is all zero, disable VDMs; if any of #W is non-zerom, failing validity checks (non-decreasing VID Compares) will fail the IPL. - WOF enablement needs IQ to fill out the OCC parameter block. If not present, WOF is disabled. Longer term (future commit), RESCLKs and VDMs will also gate WOF but not for early development and testing. - Add a Chip EC attribute to discern the DD levels that WOF is supported - Move to IVRM vs IVRMS - Made all *ENABLED HWP attributes PROC_CHIP in scope to avoid collisions from multiple chip targets - Made all HWP attributes writeable - Deprecate (preped rename) an HWP attribute - Added throttle control attributes Change-Id: I527b67c7b3111da6313c22c0af558c23e71da7bf Original-Change-Id: I5e56a36a9e2a4b3e6964ed66ff5c1013be26ed33 RTC: 173673 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40063 Dev-Ready: Gregory S. Still <stillgs@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: CHRISTOPHER M. RIEDL <cmriedl@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55524 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Undo some p9 Cumulus spy workarounds in initfilesThi Tran2018-03-131-18/+0
| | | | | | | | | | | | | | | | | Change-Id: I0b768f7fa44751fbf7867b2e03ea454b220377b3 Original-Change-Id: I961ec9e52962b1d5e1295e484922095acd6697a8 RTC:174656 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41234 Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55523 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Cumulus initfile update for OBUS & XBUS PLLsSoma BhanuTej2018-03-131-0/+18
| | | | | | | | | | | | | | | | Change-Id: Iea4f597ee6d58d8fc5d700bbc1273a69d77fc995 Original-Change-Id: I81e288c9160036bb3768c9172e860293f325a8d3 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41099 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55522 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* adjusted mem 2400 nest 1600 workaround and make dd1 onlyShelton Leung2018-03-131-0/+17
| | | | | | | | | | | | | | | | | | Change-Id: I23f74b4c525ac37460f5fb1a7b8fff16863ae314 Original-Change-Id: Iabf4b8a03eb2ae6c97ed2b6c96a0f6eed190fba6 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41128 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Dev-Ready: SHELTON LEUNG <sleung@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55521 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* P9 Cumulus InitCompiler supportis - Part 3Thi Tran2018-03-131-4/+5
| | | | | | | | | | | | | | | | | | | | | - Update *.mk files to support p9c chip ID - Workaround some spy issues p9c 10 engd issues - Fix bug to allow compilation without ENGD Change-Id: I9ba7057ddf5271a633bb87d8aa4df3a4b572d153 Original-Change-Id: Ie94b55c93081108668725d3ee9b88bd34eaa794f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40904 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Richard J. Knight <rjknight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55520 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* future proof EC feature attributes, add missing P9N DD2 initsJoe McGill2018-03-131-153/+130
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | redefine EC feature attributes, using inverse logic where required, to qualify inits specific to P9N DD1 where possible, to eliminate need for updates for future chips in plan attempt to remove usage of generic P9N_DD1_SPY_NAMES and P9N_DD2_SPY_NAMES attributes added to support initial P9NDD2 engineering data -- several spies were not being set as a result ----------------- initfile updates: ----------------- p9.cme.scan.initfile add HW391162, SCAN_SICR_TLBIE_QUIESCE feature attributes p9.core.common.scan.initfile remove fused core init, it was applying scan default for P9N DD1 and is not needed for P9N DD2+ given fuse controls p9.core.scan.initfile add CORE_P9NDD1 to qualify P9N DD1 specific register hierarchy and dial programming replace usage of P9N_DD1_SPY_NAMES, P9N_DD2_SPY_NAMES using CORE_P9NDD1 and inverse, to pick up initial pass at P9C DD1 inits p9.cxa.scom.initfile add CXA_P9NDD1_SPY_NAMES to qualify P9N DD1 specific register hierarchy p9.ddrphy.scom.initfile add DDRPHY_P9NDD1_SPY_NAMES to qualify P9N DD1 specific register hierarchy p9.dpll.scan.initfile remove POSTDD1N_DPLL_SETTINGS feature attribute, use DD1_DPLL_SETTINGS attribute and inverse to drive inits p9.l2.scan.initfile invert definition of OPTIMAL_LARX_STCX_PERF, HW409069 feature attributes p9.l3.scan.initfile p9.l3.scom.initifle remove OPTIMAL_LCO_SCOM, HW396230_SCOM feature attributes use HW386657, HW396230 attributes to drive inits p9.mca.scom.initfile add MCA_P9NDD1_ASYNC to differentiate asynchronous boundary crossing programming and dial name differences between P9N DD1, P9N DD2 p9.mmu.scan.initfile p9.mmu.scom.initfile invert definition of NMMU_DMT_DD2, NMMU_ISS734_DD2_1 feature attributes p9.ncu.scan.initfile p9.ncu.scom.initifle remove HW396230_SCOM, use HW396230 attribute to drive inits p9.npu.scom.initfile remove usage of P9N_DD1_SPY_NAMES, refactor CONFIG_ENABLE_PBUS specification to work for both P9NDD1, P9NDD2 ENGD p9.obus.scan.initfile remove EC qualification of OBUS FIR mask for simulation sample.ec.scan.initfile remove testcase requiring use of P9N_DD1_SPY_NAMES, properties of testcase are covered by other tests ----------------- HWP updates: ----------------- p9_xip_customize add customization of epsilon attributes for NMMU application p9_chiplet_scominit invert definition of P9_NDL_IOVALID feature attribute remove usage of P9N_DD1_SPY_NAMES p9_npu_scominit replace usage of P9N_DD1_SPY_NAMES with SETUP_BARS_NPU_DD1_ADDR p9_sbe_tracearray invert definition of CORE_TRACE_SCOMABLE feature attribute p9_sim_get_nia remove usage of P9N_DD1_SPY_NAMES, directly process CT/EC attributes (ok as this HWP is used for VBU sim only and not consumed by FW) Change-Id: I3269e9945cb9ef04dfd597e9c6f40d5ac3f01b0d Original-Change-Id: I63bfe8a4bfb8824b94e35a3688a6c69eecc1cf01 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40911 Reviewed-by: SHELTON LEUNG <sleung@us.ibm.com> Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55519 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* jgr17050500 Added Centaur and DMI IO SCOM initfilesJohn Rell2018-03-131-0/+18
| | | | | | | | | | | | | | | | Change-Id: I7e036d07bbb94cee5ecbef7d2a332a6aa5fd13b2 Original-Change-Id: I66e57795b5f9ca8c39ed244c7590a31e0c4cd79f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40154 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Richard J. Knight <rjknight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55518 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Update core inits for DD2Nick Klazynski2018-03-131-5/+314
| | | | | | | | | | | | | | | | | | | | Added update for new eng data Added missing spys to enable LSU trace Change-Id: If3d64ae9d97725dd8de478a542f49876854fbf37 Original-Change-Id: Iaed4992c45668c3da7cc692a3ccd02f6d1a5920a Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40380 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55517 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Updated memory DD1 vs DD2 attributeStephen Glancy2018-03-131-2/+2
| | | | | | | | | | | | | | | | | | Change-Id: If7395dc72ab91c14240037aa1f15d2e76e3bcd09 Original-Change-Id: Ie6d0f188a2ce94375535b0bf16c8ed1756558e5f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40632 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55516 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* L3 updates -- p9_build_smp, p9_fbc_utilsJoe McGill2018-03-131-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | p9_build_smp: constrain FFDC collection at 16 chips (current max size for P9 based systems) scrub node references, replace with group clarify X link requirements based on pump mode review and complete callouts p9_fbc_utils: add feature attribute to support pb_init sampling on NDD2+ replace locally defined bit constants with SCOM header file constants Change-Id: Icb2a2d4ab67a18537048ffef12203a1642efae06 Original-Change-Id: Ib1f71488ffd07580a647709d9227112f7d73384f CQ: HW328175 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40308 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: DHRUVARAJ SUBHASH CHANDRAN <dhruvaraj@in.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55515 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Adds DCD calibration control attributesStephen Glancy2018-03-131-0/+17
| | | | | | | | | | | | | | | | | | | Change-Id: Ifef1f631e84e2a46254968b844356e474ac0f8be Original-Change-Id: I2c3783eba2e5638e20136494ad897b420737566e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40178 Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55514 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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