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* Added read ctr bad delay workaroundStephen Glancy2018-03-131-0/+17
| | | | | | | | | | | | | | | | | | | | | | | The workaround finds the median and moves delays below a specified percentage of this median to be the median value. Change-Id: I1c88ccb9bd2fb07477994bf8bad2249db9f3084a Original-Change-Id: I058c61a1e7734771ab31be3f48760030fbf945b5 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39178 Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com> Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55493 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* HW407123: Slow down xlink command rate for Nimbus DD1/2Jenny Huynh2018-03-131-0/+19
| | | | | | | | | | | | | | | | Change-Id: Ib4ef0db1bb8ac9540f0f510c871a438065ca59d2 Original-Change-Id: I5e1d5f6ff0b0139765d1dc30636cec30b91e37d6 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39132 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: DANIEL C. HOWE <dchowe@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55492 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Update filter pll settings as per HW407180Ben Gass2018-03-131-0/+18
| | | | | | | | | | | | | | | | | | | | | Nimbus dd2 and Cumulus use the same settings attribute indicates Nimbus dd1 settings. Change-Id: I42b389e50db1fd9addbf91725cf3e0f5fac81d3a Original-Change-Id: Ib54038a0e1389fe0ec812f9fefe14d55473c5c67 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38847 Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Ann C. Wu <annchen@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Brent Wieman <bwieman@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55491 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Fix for HW397129-set bit 52 in the ALTD_OPTION reg to keep MC fastpath enabledCHRISTINA L. GRAVES2018-03-131-0/+18
| | | | | | | | | | | | | | | Change-Id: Ic863c0dd3197dcd5a6aa648c666de504079e512e Original-Change-Id: Ifd5be240823ea2ba4fdb6950404b429e33363bd8 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36466 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55490 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Updating L3 LCO watermarks for HW406803Luke Murray2018-03-131-0/+17
| | | | | | | | | | | | | | | | | | | | | | In DD1 there is a bug in how the LCO home region is calculated so that the wrong bit44 vaule might be used. In the long run this works out to about half of the LCO home region being dropped. To help mitigate this, we're halfing watermarks for LCO's. Change-Id: I3a38b06bd4520a24b8634facaa732baa5e008ecd Original-Change-Id: I0d64d0e4a2bb72e1a413dc03612fc6e669b56be5 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38874 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: ALEXANDER M. TAFT <amtaft@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55489 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Adding good LCO settings to initfileLuke Murray2018-03-131-0/+41
| | | | | | | | | | | | | | | | | | | | Adding dials that give good roll out of the LCO's. Changing the count for the L3 LRU and turing on decrement mode with 1/4 prob. Change-Id: I495e7d13759fe3496f936e9b71c3d5686d2e4559 Original-Change-Id: Ib35475f5c1ce68d91a2cde44d8dcdc9a715f1361 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38380 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: ALEXANDER M. TAFT <amtaft@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55488 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* update DPLL and IVRM initsJoe McGill2018-03-131-0/+55
| | | | | | | | | | | | | | | | | | | | | | | create new EQ analog specific scan initfile shift application of eq_ana_func ring from cache_initf->cache_dpll_initf adjust DPLL FF slew rate add EC feature attributes for DD1 controls Change-Id: I03389ba59253aff06a142b2232f80c6838af3601 Original-Change-Id: I0000927e946f59e29f312dc9d5b5155676bb5d3c RTC: 170960 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37370 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55487 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* p9_sbe_chiplet_reset,p9_sbe_arrayinitAnusha Reddy Rangareddygari2018-03-131-0/+33
| | | | | | | | | | | | | | | | | | | | | | * assert SCAN_CLK_USE_EVEN=1 in OPCG_REG1 in cumulus chip MC chiplet * Cumulus only dropping MC chiplet fence during arrayinit Change-Id: I9071c43712c88fa1dcf6a3484410bcb7fc04c4ae Original-Change-Id: Id339b8707cb2caac62068bdea1c93465b43721e2 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38028 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55486 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* disable noise window for DD1 HW406577Shelton Leung2018-03-131-0/+17
| | | | | | | | | | | | | | | | | Change-Id: I1fdc5342507ca5bf47ded2b579549befbdc3c463 Original-Change-Id: Iff2cdae61e72f9ebdc020a730bc3d8ffd5b23118 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38313 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55485 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Attribute support of customization of Nimbus DD1 PCI reference clock speed.Thi Tran2018-03-131-2/+2
| | | | | | | | | | | | | | | | Change-Id: I9ddd9688087f38a27cdb9962f0791ce838e8d2b6 Original-Change-Id: I5bb1646868fca15aca744b311ab5d2bc5dd64739 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38297 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55484 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* HW406130: Reduce dma read requests from 16->8 in NX initsJenny Huynh2018-03-131-0/+18
| | | | | | | | | | | | | | | | | Change-Id: I530fb30145966aaea7de6751eb93e15f3ef3b32f Original-Change-Id: I194a441cda9076cddc5888dda20478677fa7a890 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38234 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55483 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Add risklevel for HW399624 due to perf penalty; Add HW405851Nick Klazynski2018-03-131-0/+17
| | | | | | | | | | | | | | | | | Change-Id: Icfb7c1cbbbeefef509a8182309055b7acc019ffa Original-Change-Id: Ib086218882ea5b8a32aa90ba55a4c1069ca461fc Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37999 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55482 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* p9_abist: Support for p9ndd2Markus Dobler2018-03-131-0/+17
| | | | | | | | | | | | | | | | | | | | | * sdis_n workaround also in dd2 * different bits for edram_done, sram_done in dd2 * option to stop RUNN (only works in dd2) Change-Id: If5167d80f4fad7b8261990b53a769f2d94465900 Original-Change-Id: I0bda7b431b87f59d1307329bcdffd0458818cb10 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37660 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph E. Dery <dery@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55481 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Add ec_abst ring to p9n.hw_imageThi Tran2018-03-131-0/+17
| | | | | | | | | | | | | | | | Change-Id: Iacd5a679b4597c7d2271a724eced3c5fdd55c960 Original-Change-Id: Ic6fc899956e0690f75224471917ff904aa03713e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37768 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55480 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* HW405413 : NCU sends data out of orderAlex Taft2018-03-131-0/+17
| | | | | | | | | | | | | | | | | | Serializes the data. Apply to DD1 only and risk_level 0 Change-Id: I8d354124fee8ed17132a85e1f517d66af4b85a5d Original-Change-Id: I4aa5d35b04afec2c20c7f6ea5d732210d1fe2f97 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37643 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55479 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Scrubbing needs to stay off for DD2, bug HW405443Juan Medina2018-03-131-1/+2
| | | | | | | | | | | | | | | | Change-Id: Ia179fd420eb0f189b70b67a217c816914b90d969 Original-Change-Id: I1421f90e1e6fe4b1e8cd73a9124daddade4026c8 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37666 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55478 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* PM: GPE timer fix (HW389045 - Update Shadow copy of TSEL)Greg Still2018-03-131-0/+17
| | | | | | | | | | | | | | | | | | | | - Tested in Cronus with U.H to pick up init from hw_image. - For Firmware, this change is needed in the SBE image!!!! Change-Id: I555f1633fc054ed80fa0ffbf60742ccac1c1515a Original-Change-Id: Ia8b087db972f6974d1ef6fbbda5dc4fb92e41693 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37508 Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Dev-Ready: Joachim Fenkes <fenkes@de.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55477 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Set NDL IOValids based on configured NV links.Ben Gass2018-03-131-0/+36
| | | | | | | | | | | | | | | | Change-Id: Ib6466ca54afa0ff54bb1fba651945fc6ff963e95 Original-Change-Id: I8dfc5410f4f4e6ec4b6fc6dc16b54b99da8f1641 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37375 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: DARREN J. DUFFY <darren@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55476 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* p9_start_cbs updatesAnusha Reddy Rangareddygari2018-03-131-0/+18
| | | | | | | | | | | | | | | | | | | | | | | Adding delay to wait for PibReset to complete Change-Id: I4faac50060bd4c53e7000cbb74559984cff03c0f Original-Change-Id: I79c9f591102c0114810348647c38d4b7fb762076 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37161 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Dev-Ready: Kahn C. Evans <kahnevan@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55475 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* enable prefetch drop for better MC fairnessShelton Leung2018-03-131-1/+18
| | | | | | | | | | | | | | | | Change-Id: I45f9a126102ff519866a794a76deef780a92a97b Original-Change-Id: I0fee2fe19b703e090ad2364a2a38dac31079b38f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37010 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55474 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Reducing rng pace rate from 2000 -> 300 for HW403701Jenny Huynh2018-03-131-0/+17
| | | | | | | | | | | | | | | | | Change-Id: I3c444f9e1a67cce76e06fbb9b6bf0a3b85104180 Original-Change-Id: I263cf15a6fa3a375590c813536f4b52ce915c4bd Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36919 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: CHRISTOPHER D. HANUDEL <chanudel@us.ibm.com> Dev-Ready: CHRISTOPHER D. HANUDEL <chanudel@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55473 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Updates to run HW VREF cal by defaultStephen Glancy2018-03-131-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | This code runs the HW VREF calibrations (both WR and RD VREF) by default if it is supported by the HW. Four new attributes are added to handle whether HW VREF cal should be run and with what overrides it needs to be run. Change-Id: Id2467101546ddb82cb19246b91748ab19a29a3a7 Original-Change-Id: I3ed63794e955ee8c94cffce0b98dba58886e4a9d Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36803 Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Brian R. Silver <bsilver@us.ibm.com> Reviewed-by: RYAN P. KING <rpking@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55472 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* adjust SRAM timingsJoe McGill2018-03-131-19/+2
| | | | | | | | | | | | | | | | | Change-Id: If386ea2a763d5aa4edf86fccfcbe0623716fa4bd Original-Change-Id: Iae2a281eeebe46f316dc4c7d23e869f103b88abb Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36892 Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: ALEXANDER M. TAFT <amtaft@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55471 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* New dummy pulse pok bits (for L2/L3)Alex Taft2018-03-131-0/+34
| | | | | | | | | | | | | | | | | | | CAY_L2C_A102_MAC & CAY_L3DIR_MAC L2 cache and L3 Dir/Lru arrays. Change-Id: Iaab90a2e3e1286068f0a9a4c03761f3057bffc13 Original-Change-Id: Ib1912c9382a4cd5ce14488683b9b145a0f472d7b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36819 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55470 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* NPU scan/scom init updatesRyan Black2018-03-131-0/+17
| | | | | | | | | | | | | | | | | | | | | | | p9.npu.scan.initfile initial release, mask updates for HW403585 p9_npu_scominit configure XTS ATRMISS register Change-Id: Ib0019d6cc2d545729f7fa44b90e9e763c3c3b864 Original-Change-Id: Id77aad7833a7fe0c3ab2cf0710a63b215a966a80 CQ: HW403585 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36393 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: RYAN BLACK <rblack@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55469 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Add three WATs, remove IMC2, replace stop2 workaroundNick Klazynski2018-03-131-1/+52
| | | | | | | | | | | | | | | Change-Id: Ifec99257c8dcd33de469e69d201e45b3717c8734 Original-Change-Id: Idb63b61235cfbb7ac3345f6f1e3c0b5dd4738a50 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36735 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55468 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Add workaround for DDRPHY ODT config register erratum (ODT2, ODT3 bits swapped)Louis Stermole2018-03-131-0/+20
| | | | | | | | | | | | | | | | | | Change-Id: I8200ca88f315521bb8e24bb1f6d85f30fe6d9841 Original-Change-Id: If02e5e31c768c62bbdf37c15b5146bacaaf38d80 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36173 Dev-Ready: Louis Stermole <stermole@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Brent Wieman <bwieman@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55467 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Workaround to fix issue where Powerbus loses track of EQs in DD1Raja Das2018-03-131-0/+16
| | | | | | | | | | | | | | | | Change-Id: Id52995a6f2c07d0316b3879f42ae44c3a0a5089c Original-Change-Id: Ia7ffcfdead79e859f21b95be183af05949e68579 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36276 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: YUE DU <daviddu@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55466 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* reverting FIRs to master values, setting only bit 8Juan Medina2018-03-131-0/+19
| | | | | | | | | | | | | | | Change-Id: I2a7bf888fb2caa1f935fb782accec630ffd0921b Original-Change-Id: I9ff37faffad1c6c2323c501a5c55992a81fc9fd8 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35575 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55465 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* adding insert for soft fail threshold for dd1 and dd2Joshua Hannan2018-03-131-0/+17
| | | | | | | | | | | | | | | | | | Change-Id: I854222d63e0a6157cdcca476f8540e2b104a2436 Original-Change-Id: I4d3be984693aa758874ee22761c55f7508cd0ff9 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36301 Dev-Ready: CHRISTOPHER D. HANUDEL <chanudel@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: CHRISTINA L. GRAVES <clgraves@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55464 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* WAs for HW401811 HW402145 HW403465; DIS_MULTIPLE_TBLW on all modesNick Klazynski2018-03-131-2/+53
| | | | | | | | | | | | | | | | Change-Id: Ib3bb6737f27dee228a91a720a96e02a445314aff Original-Change-Id: I6a6803cc0f3571d41ae3e5fa501b89609b88d525 CQ: HW401811 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36063 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55463 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* amo cache disabled for dd1 for HW401780Shelton Leung2018-03-131-0/+17
| | | | | | | | | | | | | | | | | Change-Id: I611078d7d80cc600a88764f117a17b1298b521b1 Original-Change-Id: Iad3918c1d7e54b55ecc61f6d66181f0c05b1064a Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35839 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55462 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Adding HW363780 to NPU scom initfilesJenny Huynh2018-03-131-0/+18
| | | | | | | | | | | | | | | | | | | NPU fir bit can fire for any rcmd snoop that misses in the table lookup. Masking for nimbus dd1 only. Change-Id: Id1ad911a2b5057e5ac6a6fd0a612edc79d1e08bd Original-Change-Id: I0651b37279b0cee4ca5d383d83f0eb1079b75bd1 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35676 Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55461 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* workarounds for HW399919 HW400898 HW398269 HW398269 HW399765Nick Klazynski2018-03-131-0/+137
| | | | | | | | | | | | | | | | | Change-Id: I90340acbdc7ebf105a0ab86338ef7ddbcd2f57ca Original-Change-Id: Id84495c3b83d75e8fddd4833f04ec23614d223e2 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35406 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55460 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Added periodic cal fix - fixes bad delaysStephen Glancy2018-03-131-0/+18
| | | | | | | | | | | | | | | | | | Change-Id: I60d02448f6695aca0eb2c4e7a66eeebe62655acf Original-Change-Id: I8c55c2947dd85cc9ada45aaa9225ce641633f259 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35239 Reviewed-by: Brian R. Silver <bsilver@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com> Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55459 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* workaround for hw400932 atag corruptin in prespShelton Leung2018-03-131-0/+17
| | | | | | | | | | | | | | | | | Change-Id: I084b69293c5775524d113e81632d0580b5e90699 Original-Change-Id: I4a90407ed6fbf4bb9dbf64ee7e9c26b1e179784b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35287 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: DAVID M. KAUER <dmkauer@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55458 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* dd1 workaround for hw400075 coherency errorShelton Leung2018-03-131-0/+17
| | | | | | | | | | | | | | | | Change-Id: I13ea2522aff1b9a33a3a9d8b6c9eeeb62dced822 Original-Change-Id: I09ba40e8b92f7800a4843ff562cea3fbb75383c5 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35235 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com> Reviewed-by: Brian R. Silver <bsilver@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55457 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* VITAL cleaning for DD2Anusha Reddy Rangareddygari2018-03-131-19/+1
| | | | | | | | | | | | | | | | | | cq : HW399324 Change-Id: I14b9f49605d131b01c648536e4967bc236d82d60 Original-Change-Id: I4236b25b2587cb9705632dd55077c79e3d5cf246 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34827 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Abhishek Agarwal <abagarw8@in.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55456 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* p9.core.scan.initfile -- mask local error from CC in EC perv LFIRJoe McGill2018-03-131-0/+17
| | | | | | | | | | | | | | | Change-Id: Ic715c285a634a213e559236b526bb5936edecb4e Original-Change-Id: I1176cf9eba88a9f4f0b0309d15a44c45caf73ef9 CQ: HW401249 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35231 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55455 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* p9_sbe_tp_chiplet_init3 -- disable TP TOD hang pulseJoe McGill2018-03-131-0/+17
| | | | | | | | | | | | | | | Change-Id: I3522de333ddaac3bc4cd840fa695b6cd6681ecf5 Original-Change-Id: I838703170232b7ad39ae752f0fcde996f5bd577e CQ: HW401184 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35199 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55454 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Updating P9 L2 scan initfile to use attributesLuke Murray2018-03-131-0/+34
| | | | | | | | | | | | | | | | | | Change-Id: I6614698bb317604e138211dac24bff9301d22027 Original-Change-Id: I8aa808d2f0f3af8325af6900a0ec9fd5521183e5 RTC: 167767 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35194 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55453 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* FBC updates for HW383616, HW384245Joe McGill2018-03-131-0/+36
| | | | | | | | | | | | | | | | | | Change-Id: Ibeb804579c406e69a2046feba015981187d4e26f Original-Change-Id: I3b65925b1cadb6f4db5d64868f997ebf4ff7e625 CQ: HW383616 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34810 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: DANIEL C. HOWE <dchowe@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55452 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Adding skip group dials for cache when chip=groupLuke Murray2018-03-131-0/+41
| | | | | | | | | | | | | | | | | | | | | | The L2 dial is a scomable dial for DD1, but the NCU and L3 dials are not scan only for DD1. So the NCU and L3 have two dials one used in DD1 and one for after DD1. Change-Id: I89d566ba2291ebc8305b0711563800f4b2be5b62 Original-Change-Id: Ica63b417ae79b3b5a230c8034fd6f76b982df23b RTC: 167679 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34857 Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: ALEXANDER M. TAFT <amtaft@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55451 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Adding chip_ec_feature attributes for dd2 buildBen Gass2018-03-131-0/+1312
| | | | | | | | | | | | | | | | | | | | Resulting dd10 hw_image file matches the one generated from initfiles in master. Grub boots with resulting image and procedures. Change-Id: I7503e6031618d07684d8040f0b89b7e900f406ed Original-Change-Id: I2257448a7dcdb6be44da6196da847cca8ad4077d Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34736 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55450 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* add SS PLL settings to support 94 MHz PCI operationJoe McGill2018-03-131-0/+18
| | | | | | | | | | | | | | | | | support PCIE on DD1.x by lowering input refclock Change-Id: I553939495d62da9da7d8a68dd801196830c3dfa7 Original-Change-Id: Ic69f0b4cdcba9d667d08aa37aced6dbc4c156c98 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34389 Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55449 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* p9_getecid -- set PCIE DD1.0x workaround attributesJoe McGill2018-03-131-0/+34
| | | | | | | | | | | | | | | Change-Id: I0850f6ba81938ac4a68970197feca40e1cf607e1 Original-Change-Id: Ibef138e8d727c55ee564ffe2ee422fc79550162e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34676 Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55448 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Add MSS customization support from CRP0 Lx MVPDJoe McGill2018-03-131-35/+1
| | | | | | | | | | | | | | | | | | | | Keyword V0 offsets are the same as V1 Move bad-bits error processing to 1.03 Change-Id: I89d354b967133d0a2f3676e701f39ef03486d0be Original-Change-Id: I01e44c83f775b77e4ecc7afd7a5d92db524dfc98 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34073 Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55447 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Security control override disable support - p9_setup_sbe_configSoma BhanuTej2018-03-131-18/+0
| | | | | | | | | | | | | | | | Change-Id: If64e95c6fcb28822b60ca1e5954fe5eab09dc102 Original-Change-Id: Ia36d3ed31614976c25bef144c45396f577f037b7 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33401 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55446 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* p9.fbc.scan.initfile -- clock off MCSYNC staging latchesJoe McGill2018-03-131-0/+18
| | | | | | | | | | | | | | Change-Id: If9b88f0ee98e20fbf40b721db947af29ccdb0c8b Original-Change-Id: I7004f226a353e9075e8fe32e3bc157a58c36b4b5 CQ: HW397255 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33952 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55445 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* HW396520: DD1 workaround skip flushmode inhibit drop in cache hwpYue Du2018-03-131-0/+17
| | | | | | | | | | | | | | | | | Change-Id: I3f5ed727acc9bf5d2a554eb0eba2dcdb76faa388 Original-Change-Id: I6575ec51a94024708611678bee7af0cf7819b206 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33362 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com> Reviewed-by: ADAM S. HALE <ashale@us.ibm.com> Dev-Ready: ADAM S. HALE <ashale@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55444 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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