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* Enabling L2 64B store predictionLuke C. Murray2018-03-131-0/+17
| | | | | | | | | | | | | | | | | | | | | Turning on the 64B store prediction inside the L2. This is a performance fix. Change-Id: If6f1da065f7ee74dfb7298eec28be3e23b6c9626 Original-Change-Id: I2e91747e2cf420ffa50efeb73b8876e54c89b8d6 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50531 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55602 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* p9.npu.scom.initfile -- fix cq_sm allocation issue at low water markRyan Black2018-03-131-0/+24
| | | | | | | | | | | | | | | | | | | Change-Id: I0a83730298db3cb3a8898f4165748a29516946e7 Original-Change-Id: Ibf7f3276279e99e82841d2a209230ce38081c419 CQ: HW426816 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50480 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55601 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Nimbus DD2.2 core chickenswitchesNick Klazynski2018-03-131-1/+136
| | | | | | | | | | | | | | | | | | Change-Id: Ie3afb752063e4b802707f37ad495a9c3ecdac99e Original-Change-Id: I209bf1735b7107303bbd9009d7c99201809ba8bf Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50315 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55600 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Adding attribute to turn memory early data onLuke C. Murray2018-03-131-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Performance wants a way to turn memory early data on & off using just scoms. Adding one attribute to control all the needed scoms and defaulting everything so that early data is off. For the L3 disable cp_me by default using scom Changing the scom cp_me dial to disable cp_me for all systems after Nimbus DD2.0. This is expected to be the correct setup for most systems. We didn't disable the cp_me at the scan, because the scom can only disable cp_me if ON or allow the scan setting if set OFF. Some systems might want cp_me enabled by only changing a scom. So the default is to set cp_me on at the scan and off a the scom. This way only the scom has to be turned off to enable cp_me. Also update three scoms in the memory controler that are needed for early data. Change-Id: Id27ac44631cb0d29a30e295014a11ac43034954a Original-Change-Id: Ib2106ec4b7d26cb084601f2d6eee68833b36d30b CQ: HW426419 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49261 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55599 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Chip address extension workaround for HW423589 (option2), part1Joe McGill2018-03-131-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | chip_ec_attributes.xml nest_attributes.xml p9_sbe_attributes.xml add ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE, defines set of chips which physically support the feature add ATTR_CHIP_EC_FEATURE_HW423589_OPTION2, defines set of chips which need extended address workaround for MCD issue (applied only to Nimbus EC 21) add ATTR_MAX_INTERLEAVE_GROUP_SIZE, to restrict maximum size of memory groups formed. Written by p9_mss_eff_grouping. For HW423589_OPTION2, this will default to 512GB add ATTR_FABRIC_ADDR_EXTENSION_[GROUP|CHIP]_ID, to hold extended address configuration. Written by p9_sbe_fabricinit (SBE) and p9_mss_eff_grouping (HB). For HW423589_OPTION2, this will default to 0b0000_111, consuming all chip ID bits for extended addressing. p9_fbc_utils.C p9_fbc_utils.H extend p9_fbc_utils_get_chip_base_address to support address extension, now outputs set of ranges in each msel based on ATTR_FABRIC_ADDR_EXTENSION[GROUP|CHIP]_ID maintain original function for PPE platform which requires knowledge of non-aliased base addresses only, for code size p9_mss_eff_grouping.C p9_mss_eff_grouping_errors.xml set ATTR_FABRIC_ADDR_EXTENSION[GROUP|CHIP]_ID for HB platform restrict size of groups formed for HW423589_OPTION2 p9_sbe_fabricinit.C set ATTR_FABRIC_ADDR_EXTENSION[GROUP|CHIP]_ID for SBE platform configure FBC/NMMU extended addressing registers p9_setup_bars.C p9_setup_bars_defs.H p9_setup_bars_errors.xml add general purpose support for extended address mode for HW423589_OPTION2, configure static MCD setup p9_hcode_image_defines.H p9_hcode_image_build.C customize SGPE image with address extension configuration to apply p9.cxa.scom.initfile p9.int.scom.initfile p9.l2.scom.initfile p9.l3.scom.initfile p9.ncu.scom.initfile p9.nx.scom.initfile p9.trace.scan.initfile p9.vas.scom.initfile p9_hcd_cache_scominit.C p9_hcd_cache_scominit.c p9_pcie_config.C set unit address extension configuration on supported chips p9_rng_init_phase2.C p9_sbe_scominit.C p9c_set_inband_addr.C p9_sbe_load_bootloader.C p9_sbe_mcs_setup.C adapt to alterations in p9_fbc_utils_get_chip_base_address Change-Id: I6731cc5ec940cd19441faf6367be0908fbae7cbe Original-Change-Id: I614d566c073f1169f04f647057e6e85889f1c237 CQ: HW423589 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48576 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55598 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Modify INT FIR configuration settingsDavid Kauer2018-03-131-0/+24
| | | | | | | | | | | | | | | | | | | Change-Id: I159b42e843e4692d821bebfa2d042362b9e651da Original-Change-Id: Id4c1686cb111a14bef856fc91053228ff2e490d4 CQ:HW426891 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49578 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55597 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* remove NV iovalid assertion from FW and add scan inits to resolve glsmux xstateJoe McGill2018-03-131-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | p9_sbe_chiplet_reset remove deassertion of OBUS clk async reset, shift to p9_sbe_startclock_chiplets p9_sbe_startclock_chiplets conditionally remove workaround (assert iovalid, clock, deassert iovalid) instituted to flush DL glmux select pipeline, these will be set via scan for supported chips deassert OBUS clk async reset p9_chiplet_scominit remove assertion of NV iovalid from HB p9.npu.scan.initfile alter flush state of NVDL glsmux select pipe latches to 0b10 p9.obus.scan.initfile alter flush state of IOO PHY logic to enable lane clocks clear RX_LANE_ANA_PDWN clear RX_CLKDIST_PDWN set RX_IREF_PDWN_B Change-Id: I3ae74efba822aa4fa5dba2cca9d4f25fb21415ba Original-Change-Id: Ib9d4bf18a181ed1cf55eaf92e1486c494757d657 CQ: HW404391 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50027 Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55596 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* update data token init to use scans on p9c 1.1Daniel Howe2018-03-131-3/+3
| | | | | | | | | | | | | | | | | | Change-Id: Ib4741fe9e14002052b77a9fccf5ee0cd57a1625a Original-Change-Id: I55d2926b1cd2de7fcda4a475837e1ff54b2cc229 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49537 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55595 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Allow lpc_ed for p9n 2.2 per HW418117 fixDaniel Howe2018-03-131-4/+6
| | | | | | | | | | | | | | | | | | Change-Id: I38c7dec4722578723905a351603adae72ec6fcd1 Original-Change-Id: I23eeb099239e61073659a1e4633e388f8db0a319 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49535 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55594 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* p9.filter.pll.scan.intifile -- set 0 BGoffset for P9C DD1.1Joe McGill2018-03-131-7/+0
| | | | | | | | | | | | | | | | | | Change-Id: I3c576b7213cb90f58444b3e1b2e7179682d38b73 Original-Change-Id: Ib7f554f6249db510e6c13cb871ab110a5ea4570b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49559 Reviewed-by: Ann C. Wu <annchen@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55593 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* HW425038 INT ARX timeout workaround - Updated initfiles to 49241Claus Michael Olsen2018-03-131-3/+33
| | | | | | | | | | | | | | | | | | | Change-Id: I7b90137248388c8e54bffc63a168f590c5b38d71 Original-Change-Id: I42a3601917ab4d4b32b32e03d33ffa1f8c0da25f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49608 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Dev-Ready: Kahn C. Evans <kahnevan@us.ibm.com> Reviewed-by: Richard J. Knight <rjknight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55592 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Added CI throttling support, HW init updates, and fixed a bug with tce arb.Ricardo Mata2018-03-131-0/+25
| | | | | | | | | | | | | | | | | | | Change-Id: I2681f2b574d8fd4f8e6d6cf0827a58f67a789560 Original-Change-Id: Id71511d75e526e567fd8ba6b56551adfe2806fa4 CQ: SW407851 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49390 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55591 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* HW425038 INT ARX timeout workaroundDavid Kauer2018-03-131-0/+24
| | | | | | | | | | | | | | | | | | | Change-Id: I899d4b9bcf8da2eafedd39f6370a84594b471640 Original-Change-Id: I85813e422b4bdc9f01d1f891bece26b7fd6fdbf5 CQ: HW425038 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49241 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55590 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* HW403465 applies to all chips; Revert NDD2.1 RL; add SW406970Nick Klazynski2018-03-131-23/+28
| | | | | | | | | | | | | | | | | | | | | | Per Ron Kalla's request, NDD2.1 should not use risklevel Change-Id: I0bfbd1619e0b64061234680eac642aef4937d212 Original-Change-Id: I2354c2523d760ac16f7c4c2429003ef07e58225d CQ: HW403465 CQ: SW406970 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49148 Dev-Ready: James N. Klazynski <jklazyns@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55589 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* IO, FBC updates to enable ABUS for FleetwoodJoe McGill2018-03-131-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Attributes: ------------------------------------------------------------------------------- nest_attributes.xml add ATTR_LINK_TRAIN, written by platform on X, O endpoints to specify whether half or full link should be trained add ATTR_PROC_FABRIC_LINK_ACTIVE, written by p9_fbc_eff_config_links adjust enums for ATTR_PROC_FABRIC_[XA]_ATTACHED_CHIP_CNFG, written by p9_fbc_eff_config_links add ATTR_PROC_FABRIC_[XA]_LINKS_CNFG, written by p9_fbc_eff_config_links pervasive_attributes.xml create ATTR_PROC_NPU_REGION_ENABLED to encapsulate accessibility of NPU logic domain, written by p9_chiplet_scominit chip_ec_attributes.xml add EC feature attribute controlling DL training workaround Initfiles: ------------------------------------------------------------------------------- p9.fbc.ab_hp.scom.initfile add logic to permit reset of chg_rate master dials in second phase SMP build adjust link enable expressions to reflect new ATTACHED_CHIP_CNFG enums p9.fbc.cd_hp.scom.initfile p9.fbc.no_hp.scom.initfile consume number of configured X/A links from new attribute, simple addition won't work any longer given new ATTACHED_CHIP_CNFG enums p9.fbc.ioe_dl.scom.initfile support half-link operation, based on ATTR_LINK_TRAIN on X endpoint target p9.fbc.ioe_tl.scom.initifle adjust link enable expressions to reflect new ATTACHED_CHIP_CNFG enums p9.fbc.ioo_dl.scom.initfile support half-link operation, based on ATTR_LINK_TRAIN on O endpoint target qualify OLL enablement based on use as active fabric link adjust PHY training parameters based on current lab learning p9.fbc.ioo_tl.scom.initfile adjust link enable expressions to reflect new ATTACHED_CHIP_CNFG enums support half-link operation, based on ATTACHED_CHIP_CNFG qualify TOD_ENABLE to apply only to O links carrying X traffic p9.npu.scom.initfile clear OPTICAL_IO_CONFIG when not actively using NVLINK, finer-grained updates needed to support mix of O SMP and NVLINK usage HWPs: ------------------------------------------------------------------------------- p9_io_obus_dccal execute only on links actively carrying fabric protocol p9_io_obus_linktrain p9_io_regs encapsulate PHY FIFO reset sequence needed prior to FBC DL training execution p9_chiplet_scominit p9_npu_scominit partial good updates for NPU region p9_fab_iovalid adjust iovalid manipulation/checking, as well as link delay reporting, to support half-link configuration p9_smp_link_layer support half-link configuration via ATTR_PROC_FABRIC_[XA]_ATTACHED_CHIP_CNFG implement OBUS PHY specific workarounds p9_eff_config_links update ATTR_PROC_FABRIC_[XA]_ATTACHED_CHIP_CNFG to support half-link configuration write ATTR_PROC_FABRIC_LINK_ACTIVE on X/O endpoint targets write ATTR_PROC_FABRIC_[XA]_LINKS_CNFG to reflect total number of logically configured links, for initfile consumption Istep wrappers: ------------------------------------------------------------------------------- p9_build_smp_wrap correctly loop over all system targets for second phase SMP build p9_sys_chiplet_scominit_wrap initial release Change-Id: I6254051becffe41322f07039cde99bff3eb8f950 Original-Change-Id: Ic1d87df4d3ff0feca7ac2437fa61b6d2fc4a2d68 CQ: HW419022 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43905 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: DANIEL C. HOWE <dchowe@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55588 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Add HW425526 and HW425027Nick Klazynski2018-03-131-43/+20
| | | | | | | | | | | | | | | | | | | | | | | dis_tracker_merge does not matter since dis_tracker is now enabled everywhere, so I removed it. Change-Id: Ib59b11257ac5e4f76473a7493374d3a15868bfd6 Original-Change-Id: I9eb2871eec16f167c9f7514dcb84e057e0196f90 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49003 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Dev-Ready: James N. Klazynski <jklazyns@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55587 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Turning on NCU tlbie pacing by defaultLuke C. Murray2018-03-131-0/+17
| | | | | | | | | | | | | | | | | | Change-Id: I12ccebb87e39871e84f2bf416bfd57e0cc56fb78 Original-Change-Id: I954651af59c18401a9bd5f389f86b8faf799edbd Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48817 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55586 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Axone UpdateAnusha Reddy Rangareddygari2018-03-131-0/+41
| | | | | | | | | | | | | | | | | | | | * IOF0 pll initf for Axone * Clock mux settings Change-Id: Ib4f97a2a73acf454684cbe5d4a62c27a799ac681 Original-Change-Id: I1c6350bca42fc11e8e2a93f4134ea5db76daf79e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48278 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55585 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Additional checks to p9_extract_sbe_rcSoma BhanuTej2018-03-131-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | - To detect NDD1 or other chip for seeprom & otp addr upd - pibmem program exception - otprom program exception - Use sbe_cs bit to identify the state of pk loader - Adding CBS_STATUS_REGISTERS,ROOT_CTRL_REGISTERS in xml - Using ifndef __HOSTBOOT_MODULE while read MBOX registers - Update all Non-Secure mode RC names Change-Id: Id890b3ae2ecfc1464af72acf3a86c3a656be4dd7 Original-Change-Id: Ic764bbda94d9beb023aa1861cb143bf05b8ff06a RTC: 174954 CQ: SW404908 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41738 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55584 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* VDM: p9_pstate_parameter_block check for VDM Large threshold < -32mVGreg Still2018-03-131-1/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | - filters out old VPD parts (Nim 2.01) to just disable VDM instead of using bad jump values - check only applies for #W with version < 3 to allow for future proofing - Added error log suppression EC attribute for < Nimbus 2.1. Change-Id: I52c194575c20d81b3da93f56ad7faf23ff4afe4c Original-Change-Id: Id91fc1f816b5a3da08730feb726a246d802429db CQ: SW404757 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47964 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Dev-Ready: Francesco A. Campisano <campisan@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Francesco A. Campisano <campisan@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55583 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* PLL updates for filter BG, BW including OBUS tank coreqsJoe McGill2018-03-131-2/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | p9.filter.pll.scan.initfile adjust BG offset to -1 for P9n DD2.[12], P9c DD1.1 apply BW updates to P9n DD2.2, P9c DD1.[01] p9.obus.pll.scan.initfile apply BW updates to P9n DD2.2, P9c DD1.[01] with tests 108, 109, 110 p9_frequency_buckets: default Cumulus OBUS bucket 0 to 25.625gbs chip_ec_attributes.xml add feature attributes for BG, BW controls Change-Id: Ic36d8a8b59667ec4da9716a59c9fade378ecae70 Original-Change-Id: I5e06da5267db70bb1d6e6eae066611577d32ac7b CQ: HW423532 CQ: HW423535 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48267 Reviewed-by: Ann C. Wu <annchen@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55582 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Updating L2 re-request jitter settings for CumulusLuke C. Murray2018-03-131-0/+17
| | | | | | | | | | | | | | | | | | | | Change-Id: I6bc8aee7f6882f8629aec7a9e64d1d0a34cbaf09 Original-Change-Id: I5475bdfebc117ed16e8de09443a8d263742e1d2d Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48197 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55581 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Workaround for HW421347 Scandalous PieLuke C. Murray2018-03-131-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | This was the core hang going into re-config because of L3pref unfairness in the L2 CIU between cores. Change-Id: Ia988d23c58ed26764a6e9bbd58c9953cdc4b8230 Original-Change-Id: Ic58c2e0a92e4aef0a1076b09bbdd65e9ba17421a CQ: HW421347 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48035 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Dev-Ready: James N. Klazynski <jklazyns@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55580 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* HW415883 applies to NDD2.1, Add JellyVector WAT, add HW422495, add HW421831Nick Klazynski2018-03-131-14/+15
| | | | | | | | | | | | | | | | | | | | - WAT replaces original workaround for HW419818; two dials removed Change-Id: Ic6e650701da3a109947c7f7d5f01bc14ce39e3d9 Original-Change-Id: I540aead6556278a1da3774eba2d96cb685c4e3c1 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47181 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Dev-Ready: James N. Klazynski <jklazyns@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55579 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Add workarounds for HW421426 and HW422629, Swap IMCs aroundNick Klazynski2018-03-131-0/+41
| | | | | | | | | | | | | | | | | | | | | IMC6 and IMC7 cannot be controled by software; Linux team wants the entry currently in IMC6 configurable, so it must be switched around. Change-Id: I4bc6b26eb1544aff7c62810dedc0e0961a7541c7 Original-Change-Id: Iab7779b620f82a654055fb566eed09f6608314fd Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47014 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55578 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* updates for NPU errataJoe McGill2018-03-131-2/+69
| | | | | | | | | | | | | | | | | | | | | | | p9.chip.gtpr.scan.initfile add clock gate disable for HW407330 p9.npu.scom.initfile add workarounds for HW398156, HW364887, HW372457, HW376377, HW398156 Change-Id: I3d90705a10f988fe124ebacdbd01b521c3247da2 Original-Change-Id: I48443e7c8288cfce665dbd8b00518c3e19e7116e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46237 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: RYAN BLACK <rblack@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55577 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Added Nimbus & Cumulus attributes for INT initfilesDavid Kauer2018-03-131-6/+38
| | | | | | | | | | | | | | | | | | | Change-Id: I58b7ab92a209eea952cbfdf97533e2777d6c8eb8 Original-Change-Id: Iabb14846f0cde49bfa1c5cc90ef6007df76c2140 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46430 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55576 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Increment red_waterfall for low vdn fixJacob Harvey2018-03-131-1/+19
| | | | | | | | | | | | | | | | | | | Change-Id: I9ead76313c6e2244da09661ef2d8780647b7ee0d Original-Change-Id: Iaa5dbf94fe223cdfef7ebbfe8598f98f5472c956 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46420 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Dev-Ready: JACOB L. HARVEY <jlharvey@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55575 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Core workarounds for multiple issues.Nick Klazynski2018-03-131-2/+140
| | | | | | | | | | | | | | | | | | | | | | | | | | | HW420428 HW420575 HW416161 HW419818 HW420948 HW415883 HW420860 HW416317 Change-Id: Ib5043baf0bbd9ae71828e0f1a0dd12ecf85fd757 Original-Change-Id: I1fe1eace3c8f3ec70653fcc16db882024c8e1824 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46349 Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55574 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Updates for HW416934 and HW417233Ben Gass2018-03-131-0/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicting dd1 only dials for these were removed: ATTR_CHIP_EC_FEATURE_HW396288 ATTR_CHIP_EC_FEATURE_HW399624 ATTR_CHIP_EC_FEATURE_HW393578 ATTR_CHIP_EC_FEATURE_HW403075 ATTR_CHIP_EC_FEATURE_HW393318 ATTR_CHIP_EC_FEATURE_HW394497 Work around for HW408891 is contained within HW416934 update. Change-Id: I4ef63aa0c7355a6ece539592e01125753f82b0fc Original-Change-Id: I8cb266893d802f1673f683f17fd231e17de1cfa1 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46177 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55573 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* PM: Move to chip EC based #V validity checking in p9_pstate_parameter_blockGreg Still2018-03-131-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Was always returning SUCCESS which caused p9_hcode_image_build to not properly terminate (false error logs) - Added EC feature attribute to skip #V validity checking and thus disabling pstates for Nimbus < 20 and Cumulus < 11 - Initalized wof io_size to 0. - Rebased - Added override attribute ATTR_SYSTEM_POUNDV_VALIDITY_HALT_DISABLE to disable killing the IPL upon #V validity check failure. Disables Pstates and continues. This allow the use of parts that don't have good #V for other, non-Pstate oriented purposes. Marked with new <overrideOnly/> tag. Change-Id: I3fdc8a02f16d6779723461342e4d2449989cb65a Original-Change-Id: Ia238af9758ae1fe35d39fa536d73ec41e85f9498 CQ: SW400102 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45185 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Juan R. Medina <jrmedina@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55572 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* HW415528 and HW419742Nick Klazynski2018-03-131-8/+24
| | | | | | | | | | | | | | | | Change-Id: I86bea78c7588f7ac0adb0dd0d79630cb2b416ce6 Original-Change-Id: I03cb5fa742c9d5527768d9df739fe9993808c123 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46017 Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55571 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Expanding MCU tag fifo settings to be freq dependent.Lennard Streat2018-03-131-0/+18
| | | | | | | | | | | | | | | | Change-Id: I13f647cf76ad818ffff5ec24cdc250f75417f947 Original-Change-Id: I46baeb1bb6f076c132e735724b094ee8a99e9257 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44917 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: SHELTON LEUNG <sleung@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55570 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Add updates for NDD2.1, Serialize TB, Perf workaroundsNick Klazynski2018-03-131-11/+131
| | | | | | | | | | | | | | | | Change-Id: I2b80f32a03a698daa5cf54d1c9117073165fbfee Original-Change-Id: I1f75596eb3b75f898dc8fbe174c615654e8b6aa8 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45711 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55569 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Remove logic to disable memory clocks in STR if in PD_AND_STR_CLK_STOP modeAndre Marin2018-03-131-18/+0
| | | | | | | | | | | | | | | | | | | | | | | | | Do not disable memory clocks when in STR if power control mode PD_AND_STR_CLK_STOP (ie. treat it the same as PD_AND_STR). Removing EC Chip level check since there isn't a current plan for a RIT fix. Change-Id: Ic3b3aff8868068e3997ae8af8fba53b6d7e3bd05 Original-Change-Id: I298561c39a2419ed7f92e90c9eeaf8924fc412bc CQ:HW416315 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45653 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Michael D. Pardeik <pardeik@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55568 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* ATTR_CHIP_EC_FEATURE_HW406337 support for AxoneAbhishek Agarwal2018-03-131-1/+8
| | | | | | | | | | | | | | | | Change-Id: Ib3213bb99c95ee6334ee013fa012a9ad0042dfaf Original-Change-Id: Ifce6ec07e888a51ee55f2d53bd884e7fd229c066 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45556 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55567 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* HW415692: Make workaround permanentJoachim Fenkes2018-03-131-2/+2
| | | | | | | | | | | | | | | | | | HW415692 has become a permanent erratum, so make the EC attribute match any Nimbus EC level. Change-Id: I3696620bae3323e182e7321b6c5e05f60352838b Original-Change-Id: Ib1e352f3b1252b0d9b89b76a64c27de6cc3a483e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45470 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55566 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* jgr17082300 Setting changes for HW41801 HW419305John Rell2018-03-131-0/+18
| | | | | | | | | | | | | | | | | Change-Id: I76ba390e8b59996da5c90c1363531ce4bbeea582 Original-Change-Id: I8db11be5f37f15e41e1e6d123ff2dafc87294d28 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45072 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Richard J. Knight <rjknight@us.ibm.com> Reviewed-by: Christopher W. Steffen <cwsteffen@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55565 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* disable lpc_ed in fbc to match mc settingdchowe2018-03-131-0/+25
| | | | | | | | | | | | | | | | | Change-Id: I2c20d8ddefbe8f42b1f7a7de3b61ab55f648ff13 Original-Change-Id: Ib021f9ac254d6471f86b2dda2660cf84268944ad Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44440 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55564 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Add perf inits: HW418850,HW418789; Add clockgate issue HW418738Nick Klazynski2018-03-131-0/+72
| | | | | | | | | | | | | | Change-Id: I9c3c1a8b591c8fd2996d2b22d31c01b2863d0089 Original-Change-Id: I4ecc57a12091a5c309bf33584e38dd6d247054a9 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44802 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55563 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* resolve Zeppelin DMI channel framelock issuesJoe McGill2018-03-131-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | p9_sbe_chiplet_reset p9c_mc_scom resolve HW CQ 418671 set MC CPLT_CONF1 FASTX2 ratio controls in p9_sbe_chiplet_reset need to set prior to MC chiplet clock start for proper functional operation remove from initfile p9_cen_framelock resolve HW CQ 418901 analyze captured FRTL value along with FRTL counter overflow error FIR centaur.mcs.scan.initfile cen_scominits enable MBI trace array prior to framelock, to make usable for future debug Update p9c.mc.initfile to include fix for ZCAL to help with conflicts - bgass Change-Id: I94862c5f4122e5ccafb15ac3ab9e519ea523a27e Original-Change-Id: I7897d41250b9c113adf22fe40a8ca5971bca2a6f CQ: HW418671 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44708 Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: LENNARD G. STREAT <lstreat@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55562 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Mistakenly pulled workaround for HW410212 - readd for CDD1.0Nick Klazynski2018-03-131-1/+8
| | | | | | | | | | | | | Change-Id: I374c8e72582d028a4612b449696d9040f402025d Original-Change-Id: If2d1fa278b8d614b995a07ff3da1a81d508f692c Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44748 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55561 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Reverting chickenswitches for issues fixed in Cumulus DD1.0Nick Klazynski2018-03-131-58/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Differences: HW407282 - No dial - spreadsheet says to remove? HW407065 - Removed - spreadsheet says nothing to remove? HW408512 - No dial HW408891 - Removed HW407065 - Removed HW408628 - Removed HW408917 - Removed HW409270 - Removed HW409194 - Removed HW409355 - No dial HW410212 - Removed - (HW417242) HW411571 - No dial - spreadsheet says to remove? Change-Id: I9ae0ebb66091ee771315e0f606d2981989e4d71c Original-Change-Id: I460b214240498738c0f63a1cad055d1a57cdd71f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44600 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55560 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Update core initfiles for Cumulus DD1.0Nick Klazynski2018-03-131-50/+414
| | | | | | | | | | | | | | Change-Id: I9522c91b9c94e5db71f69cd71b61b0f75a8e94d0 Original-Change-Id: I5fddc89dbb3b1759c0690c562430208429b08b4d Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44310 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55559 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Modified gen_accessors script for greater supportAndre Marin2018-03-131-0/+18
| | | | | | | | | | | | | | | | | | | | | | Added support for PROC TARGET, only creates accessors for attributes that have the mssAccessorName xml tag, added support for other non-mss attrs that don't have [port][dimm] indexes and that have target types other than MCS, MCBIST, and SYSTEM Change-Id: I4f667acd9de455a779cded183aa357b52dcf1efb Original-Change-Id: I6c76f8e7bbc0be1dade3f77f78d3371d16b609b2 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44255 Reviewed-by: Louis Stermole <stermole@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55558 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Use DD1 SW reset for XIVE unit until we get HW reset working in DD2crgeddes2018-03-131-0/+18
| | | | | | | | | | | | | | | | | | | | | This is a temporary workaround until we get the HW reset working. Currently we are having issues with the VSD tables not getting cleared correctly when Hostboot tries to initialize interrupts Change-Id: Id503cdc2c6192aaeb0ea6c25257fa04136dbc6ca Original-Change-Id: I313cb9cbba63cb0598b663c9792acf798b1c8766 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43632 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55557 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* p9.int.scom.initfile -- mask SUE FIR for Nimbus DD2Joe McGill2018-03-131-0/+17
| | | | | | | | | | | | | | | | | | Change-Id: I13ac31203e68d1759214b55f19fb7114597e534e Original-Change-Id: I8c921e4d6adf441daa6892e56fc1208081a6fb48 CQ: HW411637 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43637 Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: DAVID M. KAUER <dmkauer@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55556 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Add additional dials to risklevelNick Klazynski2018-03-131-0/+17
| | | | | | | | | | | | | | | | | Change-Id: I4a63f3333b7aaeffa023ee066ff1be61f4b98371 Original-Change-Id: I94463fc5b28d4912439431ca89aa622661ed4034 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43635 Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55555 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Remove reset_dll from scominit, enable delay line tap pointsAndre Marin2018-03-131-3/+20
| | | | | | | | | | | | | | | | | | | | | | | | reset_dll API was found to be redundant to what already exists in the initfile per John Bialas. Removed if from scominit. Also included initfile changes that John made by enabling delay line tap points Change-Id: I7f165089ee7848f0b93cb4e7d4e25b0e7d609c79 Original-Change-Id: Ide517e8dced5176d508dcb352e041e09da206a09 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43018 Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55554 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* p9.npu.scom.initfile -- FIR updates to align with RAS XML documentationJoe McGill2018-03-131-0/+35
| | | | | | | | | | | | | | | | | | | | create feature attribute to qualify FIR2 inits update FIR2 XML,inits based on current review feedback Change-Id: I32ea02b4facd6f3e9b20dcd549660157f303eca2 Original-Change-Id: I8a1a8a92e4f4ee24b308f0bb731a953f098edc72 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42910 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55553 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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