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Change-Id: If0e517a72c428b2cd5902900f13f6a3c17a68963
RTC:68487
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/4813
Tested-by: Jenkins Server
Reviewed-by: Brian H. Horton <brianh@linux.ibm.com>
Reviewed-by: Van H. Lee <vanlee@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Change-Id: Idb7a2d8d72a55f644efd0b2548eca5df5d062e6d
RTC: 47491
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/2011
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Updating the Simics level to get FSI fixes to allow multiple
chips to work. This also allows us to remove some previous
workarounds.
The new Simics build pulled in a different PNOR so needed to
disable some of the tests.
The new Simics build also modified some of the L3 objects so
changes were required to some debug tools.
Had to update the VENICE config since Ched rewired it to look
like MURANO/Tuleta.
Testing:
Verified 2-proc, 4-centaur MURANO config
Verified 2-proc, 4-centaur VENICE config
Change-Id: I6aaaf8aad2f82dbfffb8ade551d545bedaa3e048
RTC: 41305
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1066
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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- Moved common targeting code to own subtrees
- Updated many components with header file changes
- Implemented abstract pointer class
- Implemented Hostboot specific support for targeting commonality
- Changed attribute VMM base address to 4 GB (From 3 GB)
- Removed tabs, fixed > 80 character lines
Change-Id: Ie5a6956670bfa4f262f7691b4f0ce5a20ed289fe
RTC: 35569
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/909
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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