| Commit message (Collapse) | Author | Age | Files | Lines |
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The HBBL also contains the securerom code and hw keys' hash
for verification purposes. So looking for the end of the HBBL
code leaves out those sections
Change-Id: I73a1b5c50e3a5b3f642ca569b90e79dbe4c4ba1e
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35979
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Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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The HB Bootloader now owns the responsibility of selecting the
appropriate side of PNOR to use when loading the HBB image. There
is no longer a HBB pointer in the SBE image itself. This commit
removes the code that dealt with that support. There is also
some cleaning up of a few other related functions.
Change-Id: I35bfccb3590f81867d8222333cb4be66718828fa
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36358
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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- Original code was repeatedly allocating/freeing 256K chunks of
heap memory
- Other tasks in the background fragmented the allocations and
could lead to out of memory conditions on large core number
parts
- Fix is to allocation one large chunk up front and use that for
all operations
Change-Id: Ie6df7eb9ebce526d87480425e842f8d1be8d78d4
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36920
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Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Call sendPsuQuiesceSbe before doing the deviceWrite of the SBE SEEPROM
with the SBE image.
Change-Id: I6d3cec5b0430b8083acabc30bb7ff14ba5e1b56e
RTC:158899
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34994
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Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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While verifying SBE boot from both SEEPROM sides, several changes were
identified and a hack was created to fix a HWP bug.
1) Replace use of SBE::setNestFreqAttributes with use of
TARGETING::setFrequencyAttributes.
2) Update TARGETING::setFrequencyAttributes to not pass in i2cBusDiv,
but instead to calculate this value.
3) Update TARGETING::setFrequencyAttributes to find the PLL bucket for
the new nest frequency.
4) Add a call to TARGETING::setFrequencyAttributes in call_mss_freq.
5) Remove finding PLL bucket from call_host_voltage_config. It is not
required since TARGETING::setFrequencyAttributes is being called.
6) Remove SBE::setNestFreqAttributes and SBE::checkSeepromNestFreq from
sbe_update.C as they are not being used.
7) Remove various variables, fields, and parameters because they are
unneeded after work above.
8) Add hack to set SBE boot side indicator back to primary side before
doShutdown in sbe_update.C.
9) Add syncAllAttributesToFsp call before doShutdown in sbe_update.C.
10) Add attributes for the nest PLL frequency data.
Change-Id: I97ea6386eb583a71c0dbec70adb9977e749dbfd3
RTC:152404
CMVC-Prereq:1014451
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34735
Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com>
Reviewed-by: Marshall J. Wilks <mjwilks@us.ibm.com>
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Add a function to set the boot SEEPROM for the target processor based off
the setting for the master processor.
Change-Id: Ie39ca011952ea5cf10a8b752268116265cc4fabd
RTC:162326
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34022
Reviewed-by: Matt Derksen <v2cibmd@us.ibm.com>
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Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
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Change-Id: Ibe443c8c937387ffa817d22fa72365b216f42151
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33414
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Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Set NO_SBE_UPDATE in fsprelease.config.
Patch eepromdd.C to make write cycle time a minimum of 10 msec.
Find .hbbl section before attempting to append new HBBL to SBE image and
delete it if it already exists.
Use malloc rather than stack space for ring section buffer.
Fix i_maxImgSize value passed to procCustomizeSbeImg.
Fix SBE_ECC_IMG_MAX_SIZE calculation to include pad bytes.
Change-Id: I632e17851830acb1b365abc92438b0356232487c
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32487
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt Derksen <v2cibmd@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Tested-by: William G. Hoffa <wghoffa@us.ibm.com>
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Stop using FIXED_RING_BUF_SIZE, but instead use MAX_RING_BUF_SIZE.
Change-Id: I84022645fcc9d43d5eb0c6a087cd2b6ffd671700
RTC:161050
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31269
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Reviewed-by: Richard J. Knight <rjknight@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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Changed SCOM that is read to determine SBE boot side to 0x0050008
and mask for the bit to check in that SCOM to bit 17.
Change-Id: Ibec557edae338d54a0b61a2c49e746c76afa57b9
RTC:160466
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30812
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Reviewed-by: Corey V. Swenson <cswenson@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Change-Id: I529056bf1380238f5064f18b39bc09ec97e7a112
RTC: 157659
Depends-on: Idea9e3ae8d08052e960c00c225522bbe8da3ea5e
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29521
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Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Change-Id: Iabfb44d0f4fc1901c549baa5212db2e2bcf7a210
RTC: 156833
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30172
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
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Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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This story is for general clean-up after the SBE Update work.
It will be used to turn off unit test traces, make changes that
were deferred from prior reviews, finalize selection of best
cores and handling of cores for p9_xip_customize, and turn off
performUpdateActions() call in sbeupdatetest.
Change-Id: I04747bd3897d84a6b3c3c6c7791b28a0708842f9
RTC:161074
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29955
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Change-Id: Idea9e3ae8d08052e960c00c225522bbe8da3ea5e
RTC:157890
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29505
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Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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4) Bootloader-related changes associated with Story 138226: Changes
for P9 SBE.
Change-Id: If9788c3bb2b56fbbaf4f668a1e153da79ad1757f
RTC: 139757
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28276
Reviewed-by: Matt Derksen <v2cibmd@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
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Loop to run xip_customize on the pnor image for each core must still be
implemented.
This commit also enables the call of p9_xip_customize only when not in
the FSP environment.
Change-Id: Iafc04e2ba05def7794315f9178b55dd2f2de35e4
RTC:158044
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28098
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Matt Derksen <v2cibmd@us.ibm.com>
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3) Clean up TODO's in isteps 08, 09, and 10
In istep08 enable resolveProcessorSbeSeeproms call from
call_host_slave_sbe_config.C and remove findSBEInPnor call and other
processing from call_proc_check_slave_sbe_seeprom_complete.C.
In istep09 remove updateProcessorSbeSeeproms call and nest frequency
processing from call_fabric_erepair.C.
In istep10 enable updateProcessorSbeSeeproms call from
call_host_slave_sbe_update.C and enable loop to set use of xscom
in call_proc_build_smp.C.
Change-Id: I79237f530738e3088d1b3aedafdc6ad1139d21a8
RTC: 156597
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26801
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1) Compare master to master-p8 and make any necessary updates
2) Change from FAPI to FAPI2 interfaces
Change-Id: I0cc2938612c2e4206c418bfdd851a01c2c473b5b
RTC: 156465
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26096
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This commit adds a check in istep 8.1 to see if the SBE Seeproms are
programmed with the same NEST_FREQ_MHZ attribute value that the system is
currently running at. If necessary, it will update the SBE Seeproms in this
step which might result in a re-IPL.
Change-Id: I1dca7196cd02a2704a238665b73b522c9e103936
RTC:133406
Depends-on:I9bba92f55f1b67ff4a15d79113f19d39272ec72d
Backport: release-fips840
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/20229
Tested-by: Jenkins Server
Tested-by: FSP CI Jenkins
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Created new bit (UPDATE_BOTH_SIDES_OF_SBE) which
indicates to update both sides of the SBE image when
this flag is enabled
Change-Id: Ic922e7876d9e7a61dc9b7e6186390990728cbf96
RTC:123516
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/18186
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Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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PNOR code no longer uses getSbeBootSeeprom() and it makes
more sense to keep this function in the sbe component
Change-Id: Ic984f1af35fcc7346242bee03c69d16796ef7c09
RTC: 123369
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/15912
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Reviewed-by: Brian H. Horton <brianh@linux.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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- 2 TOC's per side
- side, sideless, preserved, and readOnly tags
- Determine which SEEPROM side HB booted from
- Modify gaurd code to not run when gaurd section DNE
Change-Id: I62dd27c9aa79c3111d27e647f1b66a7c938ad6e8
RTC:109398
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/14629
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Change-Id: I5664587b4f889099290ef50d50fa9ce5e580e1eb
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/11167
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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A function was added at the very end of the SBE Update procedure to
ensure that any processor continuing with the IPL has the same SBE
Image level as the Master Processor. Any processor that had an
error during the update process is also deconfigured since we can't
trust its SBE Image level.
Change-Id: Id6dd46ca71ad97ca9f0e6ba30110ea400102a3b4
RTC: 101539
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/10868
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Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Change-Id: Ia7e6552570f2da28ec3742c20da70a64877214c2
RTC:97632
CMVC-Prereq:917712
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/9257
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Reviewed-by: MIKE J. JONES <mjjones@us.ibm.com>
Reviewed-by: Donald E. Dahle <dedahle@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Re-enabling SBE Update code. Also added better trace for update
decisions and re-arranged 1 structure for ease of debugging.
Change-Id: I879a3a250b7622145a92e1b2aebaaa3075cba156
RTC:89503
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/8244
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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These updates are required before enabling hostboot to do the
SBE Updates during the IPL.
Change-Id: I2b14c1a96940f06589a5712c2126bc51e2546835
RTC: 89503
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/7555
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Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Along with some SBE Update improvements, this commit adds
additional code to re-IPL the system after an SBE Update has
taken place. NOTE: Full SBE Update code path to be
enabled with RTC 89503.
Change-Id: I6beaee026d3fc6aaa76bfc7ca387d6765754f0c3
RTC: 47033
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/6986
Tested-by: Jenkins Server
Reviewed-by: ADAM R. MUHLE <armuhle@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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This initial commit will be used to create the new SBE
directories and files. It also supports the usr functions
to find and copy SBE PNOR images. NOTE: It will not enable
Updating SBE SEEPROMs in the IPL.
Change-Id: I3f545a134493c7595ce50fd885478bbe606de472
RTC: 47032
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/6311
Tested-by: Jenkins Server
Reviewed-by: ADAM R. MUHLE <armuhle@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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