| Commit message (Collapse) | Author | Age | Files | Lines |
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This commit removes the MVPD, MEMD and CENHWIMG sections from the axone
pnor layout as they are not being used and pnor space is limited.
Along with removing the defintion in the pnor layout xml some code
changes were required to no longer attempt to load the MVPD/MEMD sections.
Change-Id: I20739e30ad497737c0a30b66cc36052c08c11de2
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/80295
Reviewed-by: Glenn Miles <milesg@ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M Crowell <dcrowell@us.ibm.com>
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In istep14, need to call magic instruction 8021
in order to exit cache contained mode when running
simics.
Change-Id: I277f07420111c0383a7d9b61bf4d1750e39126f2
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75473
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Corey V. Swenson <cswenson@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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This commits enables HOMER BAR to point to the top
of the secure memory on SMF-enabled systems. Consequently,
the HOMER image and hostboot reserved memory will
be moved to the secure memory if SMF is enabled.
Change-Id: I37c7527b06688a41e57f14b4107ff53a507ffae8
RTC: 198825
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66702
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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- There was a situation where the memory behind a proc was valid,
but there was no valid mirrored memory
- Using PROC_MIRROR_BASES_ACK in the address calculation
fixes that problem
Change-Id: Id7a134300f728d28cffeb62d9440c2301536d9ea
CQ: SW436374
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61834
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61925
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Memory VPD contents have changed since the cards have been
built so we need to provide a method to override the data
as part of a FW build. We have done the same thing
previously for the MEMD record on the Nimbus machines
so will use the same design here for SPDX.
As part of this change, the previous MEMD support was
refactored to be completely generic so a single code path
can be used for any arbitrary record.
Change-Id: I5af5e965429c881be3de0d18c82b1d7918ac9c22
CQ: SW430659
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61190
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60980
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- Use CPU_SPR_HRMOR instead of the deprecated
ATTR_HB_HRMOR_NODAL_BASE attribute when
calculating mirrored memory address
Change-Id: I04d98f92ce71ecbaeb0ca368092253b3d1811003
CQ: SW435289
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61572
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61702
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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Math was incorrect -- NODAL offset is always group 0
chip 0, no need to divide by 2
Change-Id: Ia34088121fdfa9d2a2fda6763c28cb5942ae1f3f
CQ:SW432908
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60920
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
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There are two cases where hostboot's attention is required in istep7:
- If HRMOR we booted with doesn't fall in the range of proc_mem_to_use's
memory, then the SBE is old. HB will do an sbe update and
request re-ipl
- If HB deconfigured a bunch of dimms in istep7 and ran out of memory,
then we will request a reconfig loop
Then, in istep14, we added another sanity check to make sure we have
memory as expected to prevent unexpected failure after exiting cache
contained mode.
Change-Id: I018f4ce862cc79b5d7bacbe01cc28d1d2b4fc788
CQ:SW430015
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59696
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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- Enable back once the SW427497 is integrated
- A story 192854 is created to enable it back
Change-Id: Ia24586aea45e28da4ea4be75f9dfa1a6148de2ed
RTC:192853
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58687
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-by: Roland Veloz <rveloz@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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This change implements a Centaur SCOM cache for sensitive SCOM registers. The
cache is initialized and enabled before the first Centaur SCOM, and disabled
just prior to locking down the Centaur configuration. Once the Centaur has been
locked down, the real register values are compared to the cache entries, and the
Centaur is deconfigured (not garded) on any mismatch in assumptions.
RTC: 187288
Change-Id: I7b13bfd7eb6b427aba115d6944958bf55e171008
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57532
Reviewed-by: ILYA SMIRNOV <ismirno@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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- This is only done in Simulation
Change-Id: I011ecc6ceb05613b29d8e8e38944b342622b58c0
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53310
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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We hit out-of-memory errors while trying to boot a Opal system
due to the large amount of memory used by the PM procedures
and the pinning of memory in secure mode.
Also did some other rearranging of the pinned memory sections
to get some space back.
Change-Id: I61f219d7f32871a39b236d963bae893a6ef0ce0e
CQ: SW413191
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51724
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Change-Id: I96639c0e61a101170802ba9a96cd785d0388e985
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50057
Reviewed-by: Stephen M. Cprek <smcprek@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Reviewed-by: Marshall J. Wilks <mjwilks@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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- Extends hostboot memory from 32 to 48 MB to handle large code loads
- Dump 48 MB in hostboot dump script
- Support 48 MB hostboot size in debug framework
Change-Id: I3e64e85a7e2455bc4add2f2db9b48f57db433c7d
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43735
Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com>
Reviewed-by: Stephen M. Cprek <smcprek@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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RTC:123500
Change-Id: Iae026349cff1842c37e568059c2565cf98e14aff
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41400
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: ILYA SMIRNOV <ismirno@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Firmware doesn't currently support booting in a configuration
where there is no functional memory behind the master processor
(proc0). Added an explicit check to the 'minimum hardware'
logic to account for this to avoid confusing CRESP errors when
this scenario shows up.
Change-Id: Ia9c1e1d1cb135efb58a52edfccffe66174f57a2c
CQ: SW384402
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39048
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Stephen M. Cprek <smcprek@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Change-Id: Ia7c4dfcc947bebfc26952a9788ef0443372c9c23
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32203
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt Derksen <v2cibmd@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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There are actions going into fips that trigger memory expansion
correctly. This commit removes the previous hacks so we know that
the memory expansion is working properly. NOTE that exit_cache_contained
is still trigged by a SIMICS only register. This is due to issues with
how actions are executed.
Change-Id: I71fec05def230a61996b05c647101518dafb3573
RTC: 158417
CMVC-Prereq: 1004693
CMVC-Prereq: 1005024
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29033
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Change-Id: Id377c921327940cc7b720e601dada4af2068d94e
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22177
Tested-by: Jenkins Server
Tested-by: FSP CI Jenkins
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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Story 134082 will remove this workaround code. For now it's
needed to make PHYP happy on our 2 chip model.
Change-Id: I77bac0fb020e4ac94cc5b2639cdf2be8014e6a95
RTC: 153656
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24316
Tested-by: Jenkins Server
Tested-by: FSP CI Jenkins
Reviewed-by: Manish K. Chowdhary <manichow@in.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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This commit turns on a lot of functionality for istep 14.
In addition it updates HB's attributes with the new memory fapi attributes
after this commit memory_mcs_attributes.xml , memory_spd_attributes.xml , and
p9_htm_setup_attributes.xml can be mirrored from the ekb.
RTC: 134082
Change-Id: If09e3089eef110517002abcd78d4c6368aa0a8e7
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24001
Tested-by: Jenkins Server
Tested-by: FSP CI Jenkins
Reviewed-by: Andres A. Lugo-Reyes <aalugore@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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This change includes the following:
- Kernel Updates to handle hypervisor interrupt vector
- Interrupt Resource Provider changes to setup and handle
LSI Based interrupts
- Kernel updates to handle modified interrupt flow for
LSI Based interrupts
- Attribute updates for Scom BAR Registers
Change-Id: If63f246a0090ab8c81c3fa8ac3ab6871a0af2e31
RTC:137561
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/20692
Tested-by: Jenkins Server
Tested-by: FSP CI Jenkins
Reviewed-by: Andrew J. Geissler <andrewg@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Implemented a set of macros and constants that can be used
everywhere to translate a PIR into its component parts
and pull out individual pieces of data from a complete
PIR.
Also added and updated the references to the old
ATTR_FABRIC_NODE_ID with ATTR_FABRIC_GROUP_ID.
Change-Id: If9735f53940e5849a648729e4bf8ca0cfbb09f6e
RTC: 88055
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/706
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Change-Id: Idcbcac016ec0a72d5d77106db0ac089285640633
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22894
Tested-by: Jenkins Server
Reviewed-by: WILLIAM G. HOFFA <wghoffa@us.ibm.com>
Reviewed-by: Elizabeth Liner <eliner@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Read attributes for the memory base and size
Invoke Simics action to create mainstore
Invoke Simics action to exit cache contained mode and unmap L3 cache
Change-Id: Ic8aeb7e768b4e4a0b487c1a22b069c91dfe3d674
RTC:132577
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22277
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Christian Geddes <crgeddes@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Change-Id: Idad8c430afef013a91e0c206d4fff80fc45053c0
RTC:137652
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/21501
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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