| Commit message (Collapse) | Author | Age | Files | Lines |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Rather than having to remember to include config.h anywhere
we reference a CONFIG variable (and usually forgetting),
this adds it to the default compiler flags so that it
gets included in every source file we build.
Change-Id: I53622ab4d46c55d942e98cae6ec03049fd5b3d08
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/87475
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Zachary Clark <zach@ibm.com>
Reviewed-by: Roland Veloz <rveloz@us.ibm.com>
Reviewed-by: Christian R Geddes <crgeddes@us.ibm.com>
Reviewed-by: Nicholas E Bofferding <bofferdn@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Since the OCMB chip is held in reset until after presence detection the
IDEC register cannot be read to differentiate between Gemini and
Explorer chip types. To work around this issue, during the early part of
IPL when presence detection is occurring the OCMB IDEC function will instead
read the SPD and populate the necessary attributes with what is found
there. That will be used to determine the difference between Gemini and
Explorer until later when the OCMB IDEC register can be read from. At
that point the IDEC read will be executed again and the data read from
the OCMB IDEC register will be used to cross-check the data read from
the SPD. Any discrepancies will be handled with predictive error logs.
Change-Id: Ica664b06ff3488f48253d3ef02eff2d49c5d240d
RTC: 208696
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76108
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The OCMB Explorer Chip doesn't read for IDEC but instead assumes hardcoded
values. Since the Explorer chip is held in reset until iStep 10.4, this
commit will prevent IDEC reads during discoverTargets and instead
perform the read when exp_check_for_ready() is successful.
Change-Id: I4ef5a01badb195acca0c2187ef76ea55f58eafe4
RTC:201996
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75881
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Resolve warnings when compiling with gcc 4.8. Compiled with GCC 7.3,
no more compile errors/warnings; build ends with caught exception from
linker. This commit compiles with GCC 8.2, no more error/warnings; except
for a linking warning.
Change-Id: Ib5d7c2b5bd350edc76ee2c7de96896154cd44420
RTC: 202716
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72271
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Reviewed-by: Ilya Smirnov <ismirno@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
We added P9A awhile back but forgot to add in the explorer libs.
Some of the MSS hwps are requiring these so we need to add them.
When we pulled this in it caused the HBI image for the Nimbus
and Cumulus standalone layouts to be too large. To get around this
we will not compile any Axone/Explorer HWP code in non-axone system
configurations.
Change-Id: I041f5f160a6e530995bbb1b350a1b2362704fbc8
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75224
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Reviewed-by: Corey V. Swenson <cswenson@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: Christian R. Geddes <crgeddes@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
As per P9 Axone IPL flow doc, this HWP needs to be called on every
functional OCMB targets. This is called after the p9a_ocmb_enable
hwp is called in this istep.
Change-Id: I5bab233545769f396ba35b6d61c0733a9afd9087
RTC: 195553
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71787
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Reviewed-by: Corey V. Swenson <cswenson@us.ibm.com>
Reviewed-by: Roland Veloz <rveloz@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Per IPL Flow doc for P9 Axone, p9a_ocmb_enable needs to be called
on all processors during istep 10.4
RTC: 195553
Change-Id: I50fa98959008cccfe0620c8bc6e62f33ee91c135
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71229
Reviewed-by: Roland Veloz <rveloz@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This commit uses SBEIO ChipOps to read the HW Key Hash from the
SBE Seeprom when reading from the Seeprom that booted the processor.
This will help avoid I2C collisions when both Hostboot and the SBE
try to access the same SBE Seeprom at the same time.
Change-Id: I5693cc59aa2a7259f07363328bd8513c943f0a06
CQ:SW435288
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61958
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
FSP was not IPL'ing from SBE side 1 when production key is corrupt
in SEEPROM of SBE side 0 (due to the key mismatch check). This
change gets around that by only matching SBE keys for the sides
that booted in non-MNFG case.
Change-Id: I1dfcb5c7f7e281125fdbcfc8b8f3a84747c90f59
CQ:SW420430
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60571
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com>
Reviewed-by: ILYA SMIRNOV <ismirno@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This change implements a Centaur SCOM cache for sensitive SCOM registers. The
cache is initialized and enabled before the first Centaur SCOM, and disabled
just prior to locking down the Centaur configuration. Once the Centaur has been
locked down, the real register values are compared to the cache entries, and the
Centaur is deconfigured (not garded) on any mismatch in assumptions.
RTC: 187288
Change-Id: I7b13bfd7eb6b427aba115d6944958bf55e171008
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57532
Reviewed-by: ILYA SMIRNOV <ismirno@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Always force the SUL to be on, regardless of the status of
security on the system. This will lock down the SBE SEEPROM
and prevent writes to it. Do the setting of SUL after istep 10.2
after SBE is updated.
Change-Id: If18986d709a44c8848ff31486bc1154759359c4c
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56822
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
We are going to live with the workaround we've had in place for
several years now.
Change-Id: I7966f517cac2d820dc086c163a7985112e2d0fa3
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53465
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Istep 10.3 (host_set_voltages) has been moved to Istep 8.12
and needs to be no-oped. Executing host_set_voltages twice
causes crashes due to secureboot thinking we are trying to
skip an istep. Note that validateSecuritySettings that was
performed in 10.3 has now been moved to 10.4 (with the required
sub-routines).
Change-Id: I81284157dedebb3f4ee357ce28b29b1dd6a3fe8a
CQ:SW416209
CMVC-Coreq:1044932
Backport: release-fips910
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53443
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com>
Reviewed-by: Marshall J. Wilks <mjwilks@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
|
|
|
|
|
|
|
|
|
|
| |
Change-Id: I1276ccae8d68f8c7c8b555f6ce6dd409e061076f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45136
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
|
|
p9_chiplet_scominit, move from istep 8 to istep 10
shift content required for XBUS, fabric establishment
into p9_chiplet_fabric_scominit, to be called in istep 8
p9_chiplet_enable_ridi, move from istep 8 to istep 10
shift content required for XBUS establishment
into p9_xbus_enable_ridi, to be called in istep
CMVC-Coreq: 1023401
Change-Id: I4c60e4c41211976c7919a603ab679357cc4af106
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39956
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Brent Wieman <bwieman@us.ibm.com>
Dev-Ready: Brent Wieman <bwieman@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39960
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
|