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* Fix race condition between INTR and SBEIODan Crowell2017-07-312-61/+23
| | | | | | | | | | | | | | | | | | | | | Fixed a race condition in clearing out the PSU interrupt register that existed between the INTR and SBEIO code. We can sometimes lose interrupts for SBE PSU operations which leads to a timeout. Also added code to look for SBE errors if a PSU operation times out Change-Id: I8cdcdcc08956b038bcc65ad7e00a34719bf14c61 CQ: SW396057 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43339 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Elizabeth K. Liner <eliner@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
* Set fused core enabled on the thread cntxt reg after resetting XIVE HWcrgeddes2017-07-132-0/+35
| | | | | | | | | | | | | | | | | In DD2 we are using the HW to reset the XIVE unit. We found that we need to set the fused mode enabled bit in the INT thread context register after the XIVE unit is restarted so this commit adds that to the XIVE unit reset path. Change-Id: I2c962fd67b60fc70ad431704ea83ca56eb5cb23f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42998 Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* Move disabling PSI CEC interrupts to the common path for INT resetcrgeddes2017-07-112-6/+20
| | | | | | | | | | | | | | | | | In DD1 we used a SW reset to reset the INT unit, in DD2 we will use the HW resets. In both paths we need to disable the PSI CEC intrs. This commit moves the code that disables PSI CEC interrupts to before the code paths diverge in the resetIntUnit func in intrrp.C Change-Id: I2ebdbf374e7a2561151a138c6304ef31da1af4aa Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42850 Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Matt Derksen <mderkse1@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Enable LSI interrupt after masking sources in interrupt service initcrgeddes2017-06-201-0/+2
| | | | | | | | | | | | | | | In DD2 the interrupt HW is initialized in a different state to make things safer. The idea is to prevent hot interrupts from firing when we are not ready. Change-Id: Ie31ad1f8f2dc0e5ba5bf62118f0ade8ed8097790 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42053 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Fix PVR check for Nimbus DD1Dan Crowell2017-05-111-2/+2
| | | | | | | | | | | | | | | | | | Added check for bit 18 to distinguish between Nimbus DD1.0 and Cumulus DD1.0 Consolidated Nimbus DD1 checking to a common function Added printk output that shows which CPU we're running on Modified some existing printk output to use fewer characters Change-Id: I1c42df0051fc2d9cc5fa54d95f68c3bd26b86462 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39876 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Corey V. Swenson <cswenson@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Update the interrupt routing for the Slave proccrgeddes2017-05-081-0/+13
| | | | | | | | | | | | | | | | | During Hostboot we route all interrupts to the master proc. During the MPIPL we send a PSU chip op to the SBE, if the slave isnt set up to route to the master proc then we get a xstop. This fix makes sure we update the slave proc's interrupt routing on the MPIPL path Change-Id: I41e2728e049128e631537fe016d4402264739f23 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40181 Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Remove deprecated attribute FABRIC_NODE_IDPrachi Gupta2017-04-271-4/+4
| | | | | | | | | | | Change-Id: I3bea4af0740b2dba53631fcd195a26b6102a8ba3 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34993 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Reviewed-by: Matthew A. Ploetz <maploetz@us.ibm.com>
* Disable resetting on INT unit during MPIPLcrgeddes2017-04-171-2/+15
| | | | | | | | | | | | | | | | | | | Previously we were trying to pull the thead context before clearing out the phs_thread_enabled regs when we initialized the intrrp during mpipl. However I found that attempting this is causing a recoverable fir which down the road creates a predictive gard record. We don't need to be calling this in DD1. Not sure for DD2 yet but I have a story to revist Change-Id: Ibb7d11463e80285354fda1355105cb58e2101ea7 RTC:172905 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39344 Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Create PVR routines to handle DD2 changesDan Crowell2017-03-091-5/+8
| | | | | | | | | | | | | | | Created new PVR_t structure that understands how to decode the PVR for Nimbus DD1 and future versions. Change-Id: Ie7e6f62d65fb1a3e11b1021f1600e7421b8c30a9 RTC: 160361 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37303 Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Reviewed-by: Matthew A. Ploetz <maploetz@us.ibm.com>
* Hostboot Base TCE SupportMike Baiocchi2017-03-081-23/+0
| | | | | | | | | | | | | | | | | This commit adds the base support for hostboot to enable/disable the use of TCEs. It allows for the creation and managment of a TCE table and also initializes the P9 processors to use this table. Change-Id: Idb40f9df5a90d8b7e87b2f5b745cbe7e66109df2 RTC:145071 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32562 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Stephen M. Cprek <smcprek@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Marshall J. Wilks <mjwilks@us.ibm.com> Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
* Fix up interrupt init process for MPIPLcrgeddes2017-02-222-24/+107
| | | | | | | | | | | | | | | | Pulled enableVPCPullErr out of resetIntUnit function Added disableVPCPullErr to MPIPL flow Add in enableLSIInterupts func to call after enableInterrutps Moved enableInterrupts function before maskAllInterrupts call Change-Id: I6fadabfc74a5766862ad59db5c43596aa91e3199 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36570 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Need to access XIVE Thread management area with master threadDean Sanner2017-01-121-1/+10
| | | | | | | | | | | Change-Id: I9700b328dbc96a3a746be91b9d50de3752073aae Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34530 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Clear out interrupt mask list after resetting XIVE unit for MPIPLcrgeddes2016-12-211-0/+4
| | | | | | | | | | | | | | | | | | We were seeing a bug where after resetting the XIVE unit, the register determing the mask gets cleared and the INTRRP's list of "masked" interupts is no longer valid. We have to clear it out to match what is now in the register. Change-Id: I00f01a212c09ab2efbebbc3aa119bbe5c4a29779 RTC: 166362 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34145 Reviewed-by: Matt Derksen <v2cibmd@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* Disable PSI INT during handoff to payloadDean Sanner2016-12-211-0/+7
| | | | | | | | | | Change-Id: Ieada68446c7ccf72cceb1c1610ba6e2adc2f6cbf Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34127 Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* Fix bug in MPIPL path for INTP initcrgeddes2016-12-201-3/+6
| | | | | | | | | | | | | | | | We were running setup bars on the master proc twice due to a bug in the if statement determining if a proc was master or not Change-Id: Ie0aafbc0cd4885e45420076f7d4aa8efc10d584a RTC:165369 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34059 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Matt Derksen <v2cibmd@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Perform Interrupt ACK + EOI on Master Core Thread 0Bill Hoffa2016-12-151-3/+33
| | | | | | | | | | | | Change-Id: Iaf97f5b9acedcacb0b0b06f67d445678f8daafd2 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33802 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* INTRP Reset Workaround for XIVE HW Reset Not WorkingBill Hoffa2016-12-122-137/+236
| | | | | | | | | | | | | | - Unset All Interrupt Settings - Disable Interrupt BAR Regs Change-Id: Ia5247115f53dce89b24829853eb11d7fb7e0845b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32748 Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Update INTP init for MPIPL pathcrgeddes2016-11-112-30/+94
| | | | | | | | | | | | | | | During the MPIPL path we want to reset the INTP before we start it up. This is because there could have been extra stuff lingering around from the inital IPL. Change-Id: I3db814edfc85065d546297d7bc6cb3f158c26d32 RTC:157652 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32370 Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Create function to handle External InterruptsBill Hoffa2016-11-052-76/+83
| | | | | | | | | | Change-Id: I8aa3b0f218e51c28d7e8ca106c75c3c5bfe14f87 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30912 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Mask Interrupt Sources Prior to Resetting Interrupt LogicBill Hoffa2016-10-191-3/+15
| | | | | | | | | | | Change-Id: If97c08fc1a5133c8b14c9262694235c2783c5bbf CQ: SW369405 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31492 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-by: Matthew A. Ploetz <maploetz@us.ibm.com>
* Multi-Proc Interrupt Support with Remote LSIsBill Hoffa2016-10-072-210/+653
| | | | | | | | | | | Change-Id: I8a981628cd3adc54ba581deb0ce8afb183febef3 RTC: 150562 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29719 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Handle Multiple LSI Interrupts SimultaneouslyBill Hoffa2016-09-261-31/+46
| | | | | | | | | | | | Change-Id: I1a2933ef948b370cffade723b3046f680169291a CQ: SW367219 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30197 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Matthew A. Ploetz <maploetz@us.ibm.com>
* Refactor Polling for PSU Interrupt handling by INTRPBill Hoffa2016-08-102-5/+5
| | | | | | | | | | Change-Id: I4875bf436e5b258b7cd932b370e42b12cfdeea86 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28101 Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Elizabeth K. Liner <eliner@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Matthew A. Ploetz <maploetz@us.ibm.com>
* Close timing window between PSUDD and INTRDean Sanner2016-07-071-7/+9
| | | | | | | | | | Change-Id: Ifb6ab16bbb06335c7b898c77ffe308b6ff78ef86 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23719 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-by: Matthew A. Ploetz <maploetz@us.ibm.com>
* PSIHB Interrupt Support for Multi-CoreBill Hoffa2016-06-291-3/+37
| | | | | | | | | | | | | - Added functionality to set the proper bits in the proper phys_thread_enable reg in the XIVE IC Change-Id: I7c15173debf42cf85c50a546d6d6678545ee467c Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23162 Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Disable PSI Interrupts on PSIHB during initBill Hoffa2016-06-022-14/+28
| | | | | | | | | | | | | | | - Fix interrupt masking/unmasking as it appeared the MMIO read was getting optimized out by the compiler Change-Id: Ib9aa220a489f31c7f3cd6600ec9edab3d51f00e8 CQ: SW354189 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25243 Reviewed-by: Andrew J. Geissler <andrewg@us.ibm.com> Tested-by: Jenkins Server Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Tested-by: FSP CI Jenkins Reviewed-by: Matthew A. Ploetz <maploetz@us.ibm.com>
* XIVE CAMS is 1 byte access, disable VPC Pull errorDean Sanner2016-05-263-4/+120
| | | | | | | | | Change-Id: Ie3177e8c3cadc2e927c88e07250383c312f994a7 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24281 Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
* Enable waking threads on master core with doorbell interruptsBill Hoffa2016-05-171-9/+9
| | | | | | | | | | | | | Change-Id: Iceb33f0b8c802e7448e8b77200623048f7f7ab61 RTC: 141924 CMVC-Coreq: 993299 CMVC-Prereq: 994801 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23591 Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Reviewed-by: Andrew J. Geissler <andrewg@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Doorbell Interrupt Base Support for Core/Thread WakeupBill Hoffa2016-05-062-104/+102
| | | | | | | | | | | | | | | | | | | | | | | | | This change includes: - Implementation of a generic KernelWorkItem Class - Kernel functionality for doorbell send to specific PIRs - Kernel changes to send core/thread Wakeup doorbells using doorbell_send() + placing KernelWorkItems on a cpu stack obj to be executed during doorbell wakeup - Kernel Interrupt Message handler changes to send wakeup msgs - Interrupt Resource Provider (INTRRP) Changes to handle wakeup msgs and monitor for timeouts - Changes to the IPL flow to invoke proper Core/Thread Wakeup - A basic outline (commented out) for how IPC messages can be implemented in the future Change-Id: I547fb8719bac657def561565ae11ab18cde72096 CMVC-Prereq: 992722 RTC:137564 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22815 Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Reviewed-by: Andrew J. Geissler <andrewg@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Use SBE for scoms to slave chipsMatt Derksen2016-05-041-0/+1
| | | | | | | | | | | Change-Id: I31a33c62ae502d8045882a1a4df5bcaf9f2f34ac RTC:132655 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23785 Tested-by: Jenkins Server Reviewed-by: Andrew J. Geissler <andrewg@us.ibm.com> Tested-by: FSP CI Jenkins Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Add INTRP message handling for UNREGISTER_MSG_QBill Hoffa2016-04-272-3/+30
| | | | | | | | | | | Change-Id: I9e76c07849331bf1402aeeddd32fdf1dcc26eafc RTC:151604 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23366 Tested-by: Jenkins Server Reviewed-by: Andrew J. Geissler <andrewg@us.ibm.com> Tested-by: FSP CI Jenkins Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-by: Matthew A. Ploetz <maploetz@us.ibm.com>
* Remove PSIHB ESB BAR disable workaround for simulatorBill Hoffa2016-04-211-6/+0
| | | | | | | | | | | Change-Id: I0bd9901f82cf0343b15df9962a904084f385960d RTC: 149694 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22988 Tested-by: Jenkins Server Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Tested-by: FSP CI Jenkins Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-by: Matthew A. Ploetz <maploetz@us.ibm.com>
* P9 PSIHB Base Interrupt SupportBill Hoffa2016-03-303-862/+1012
| | | | | | | | | | | | | | | | | | | This change includes the following: - Kernel Updates to handle hypervisor interrupt vector - Interrupt Resource Provider changes to setup and handle LSI Based interrupts - Kernel updates to handle modified interrupt flow for LSI Based interrupts - Attribute updates for Scom BAR Registers Change-Id: If63f246a0090ab8c81c3fa8ac3ab6871a0af2e31 RTC:137561 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/20692 Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Reviewed-by: Andrew J. Geissler <andrewg@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Update constants and comments for P9 PIR formatDan Crowell2016-02-292-28/+30
| | | | | | | | | | | | | | | Implemented a set of macros and constants that can be used everywhere to translate a PIR into its component parts and pull out individual pieces of data from a complete PIR. Also added and updated the references to the old ATTR_FABRIC_NODE_ID with ATTR_FABRIC_GROUP_ID. Change-Id: If9735f53940e5849a648729e4bf8ca0cfbb09f6e RTC: 88055 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/706 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Investigate graceful shutdown path anomoliesRichard J. Knight2015-04-241-1/+1
| | | | | | | | | | | -Fix shutdown loop to notify processes correctly -Block pnor writes when gracefull shutdown is in process Change-Id: I1d882e8596a0218fa499d947f3c6387e7ecd4ee8 RTC:125361 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/16852 Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com> Tested-by: Jenkins Server
* P8+ VPO - HB supports to istep 7 for NVLINK testThi Tran2015-01-161-0/+10
| | | | | | | | | | Change-Id: I79ec79e1601ae51bf759b80a07c5b4cf2d97fc5c RTC: 95236 Depends-On: I19823ac32a963d7072d21140b828c30ab326a19f Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/14468 Tested-by: Jenkins Server Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Fix spelling mistakes using codespell.Patrick Williams2015-01-152-8/+8
| | | | | | | | | | | | - See https://github.com/lucasdemarchi/codespell Change-Id: I03e102d1ebb9473b6226fa9b6edb684fa0218a2f Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/15031 Tested-by: Jenkins Server Reviewed-by: STEPHEN M. CPREK <smcprek@us.ibm.com> Reviewed-by: Zane Shelley <zshelle@us.ibm.com> Reviewed-by: Brian Silver <bsilver@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Use non blocking messages in intRP to prevent trace deadlockDean Sanner2014-09-112-29/+93
| | | | | | | | | | | Change-Id: I14cd978a7a102f75e4829d5daa369946e766e874 CQ: SW274049 Backport: release-fips820 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/13025 Tested-by: Jenkins Server Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Restrict timebase sync to once per core.Patrick Williams2014-07-171-2/+1
| | | | | | | | | | | | | | | | | | | | | As part of Id3a3bc0b7367e61f2725af17975fe3ba068f69a9, I fixed the deferred work queue to not leak work objects if there are multiple objects. When cores wake up, each thread inserts a work object to synchronize its timebase. Now that they are not leaking, we are running this 8 times, which is causing enough clock drift that we are getting passed the timeout for core wakeups. Modify deferred work queue to allow us to skip performing work if there is already an outstanding deferred work object. This will return us to running the timebase sync just once. Change-Id: Iccffeb9d0578dcd08d41d41ca6af1b82388e7e34 RTC: 111512 Backport: release-fips811 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/12281 Tested-by: Jenkins Server Reviewed-by: Brian Silver <bsilver@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Clean handling of shutdown path in error casesDoug Gilbert2014-07-072-4/+8
| | | | | | | | | | | Change-Id: Id03c0f2fc91a31b05572222a2a2743db1518198c RTC: 109993 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/11636 Tested-by: Jenkins Server Reviewed-by: Michael Baiocchi <baiocchi@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Corey V. Swenson <cswenson@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Change CPU_WAKEUP_SECONDS to 2Brian Silver2014-07-011-2/+5
| | | | | | | Change-Id: I92a3511beddb650675101b6f853c219cac14876e Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/11923 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Change copyright prolog for all files to Apache.Patrick Williams2014-05-215-55/+55
| | | | | | | Change-Id: I5664587b4f889099290ef50d50fa9ce5e580e1eb Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/11167 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Update makefiles & included .mk files to use += convention.Brian Silver2014-05-211-16/+16
| | | | | | | | Change-Id: I4148bc4c770b7c3c10fe25aa18d57d1a4301e5a9 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/11194 Tested-by: Jenkins Server Reviewed-by: Christopher T. Phan <cphan@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* HostBoot Interrupt RP error not being handledDoug Gilbert2014-05-081-27/+22
| | | | | | | | | Change-Id: I301e496a64e9765871b95260ab59bf2dfc9c0370 RTC:106247 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/10771 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Create SRC description file during buildDoug Gilbert2014-05-081-5/+5
| | | | | | | | Change-Id: I636dbfad6cc695e42e6de403e26a91634a4b370d Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/10715 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Remove EOIs for PCIe on MPIPLDean Sanner2014-04-032-129/+2
| | | | | | | | | Change-Id: I69fd098449410888c9358868dc3affbc16d906bb CQ: SW248383 Backport: release-fips810 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/10105 Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com> Tested-by: Jenkins Server
* Workaround invalid SBE use of IPI inject registerDean Sanner2014-03-041-0/+29
| | | | | | | | | Change-Id: I40600399daf2ef563b534bd91143a4f45d00ff79 CQ: SW248610 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/9273 Tested-by: Jenkins Server Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Extract hb_image_exist mask on multinode MPIPLDean Sanner2014-03-022-3/+89
| | | | | | | | | CQ: SW248937 Change-Id: I5a7e901b7923cd489795c28dde00538a03ff6dc5 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/8955 Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Handle pending interrupts across nodes in mpiplDoug Gilbert2014-03-023-2/+413
| | | | | | | | | RTC: 80988 Change-Id: I7ef9feaa3d163d6956576f30538e2fe001e892a1 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/8441 Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Clean up beam errors in core.Patrick Williams2014-02-271-1/+1
| | | | | | | | | | Change-Id: I695a38ae88583a052cae19b930eb53171f8fab2b RTC:94993 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/9050 Tested-by: Jenkins Server Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: Michael Baiocchi <baiocchi@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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