| Commit message (Collapse) | Author | Age | Files | Lines |
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Change-Id: I8bb100c3e57a441183b385b6d7a5efbddc4541f5
RTC:127334
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/17967
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Previously the code in fsiscom.C was grabbing the wrong bits from
the status register in order to get the correct pib callout. This
has been fixed now.
Change-Id: Ifda6303b866c3040bf76562312a90ba48aa652ca
RTC: 130912
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19282
Tested-by: Jenkins Server
Tested-by: Jenkins OP Build CI
Tested-by: Jenkins OP HW
Tested-by: FSP CI Jenkins
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Change-Id: I1e909145a28c4cce750baee5d79f8f1672235ba9
RTC: 106255
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/12841
Tested-by: Jenkins Server
Reviewed-by: Corey V. Swenson <cswenson@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Added more address-specific FFDC collection logic to handle
more specific error scenarios we've seen or talked about.
Change-Id: Ifcc2b98b9c55ed5e6a35d1556cd530438ec120c2
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/11257
Tested-by: Jenkins Server
Reviewed-by: Michael Baiocchi <baiocchi@us.ibm.com>
Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Change-Id: I5664587b4f889099290ef50d50fa9ce5e580e1eb
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/11167
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Change-Id: I4148bc4c770b7c3c10fe25aa18d57d1a4301e5a9
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/11194
Tested-by: Jenkins Server
Reviewed-by: Christopher T. Phan <cphan@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Change-Id: I05fd5c3864910eabcb014ce12b7c63a94a95a54f
RTC: 80081
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/10782
Tested-by: Jenkins Server
Reviewed-by: Corey V. Swenson <cswenson@us.ibm.com>
Reviewed-by: Michael Baiocchi <baiocchi@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Some code (PRD) chooses to commit errors from register accesses
immediately and then continue on. If the error ends up
deconfiguring a target that can then lead to even more confusing
results downstream.
Change-Id: I289b43506a6d7c9d18d4ac6792fffbfc733daea6
CQ: SW250177
Backport: release-fips810
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/9415
Tested-by: Jenkins Server
Reviewed-by: Michael Baiocchi <baiocchi@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Modified which error bits are checked in the PIB2OPB status as
well as changing a few error reset functions.
Change-Id: I27676947983f0b66c940d68bbd5f134912749ad9
CQ: SW248395
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/9238
Tested-by: Jenkins Server
Reviewed-by: Michael Baiocchi <baiocchi@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Change-Id: I5c749abf5e112fe6877b87fb242134807f4cff27
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/8744
Tested-by: Jenkins Server
Reviewed-by: Andrew J. Geissler <andrewg@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Change-Id: I1538fbf386d5480e473f3f0b049492d494412624
RTC: 35064
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/5825
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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With this code an IPL on a single DCM system makes it up into
cen_sbe_tp_chiplet_init1 before it fails due to a Centaur SBE
issue. In addition to changes in the init flow, some updates
have been made to the error recovery/logging paths.
Similar results now seen on 2-DCM system.
Change-Id: I6c4b31ee568919c81d388c99ceb26c24705da9be
RTC: 67844
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/5394
Tested-by: Jenkins Server
Reviewed-by: William H. Schwartz <whs@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Change-Id: I13a80f814fd13a30315320c0b0c7374f39c3ecc2
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/2522
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Tested-by: A. Patrick Williams III <iawillia@us.ibm.com>
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some of the constants to make them a little more consistent with
some of the other modules.
Change-Id: I56d9de9179fe088b46aaa41c6b46e06b6e4ca423
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/704
Tested-by: Jenkins Server
Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
Reviewed-by: Melissa J. Connell <missyc@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Change-Id: Ibe49dc935206775de032d397b2800a7b83208283
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/630
Tested-by: Jenkins Server
Reviewed-by: Monte K. Copeland <copelanm@us.ibm.com>
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for each chip versus a single global mutex.
RTC Story 4389
Also stuck in a quick fix for Issue 4493 at the same time.
Verified against VENICE model with a Centaur.
Change-Id: I62fc2c979315b60594104550f8095aa80996c40f
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/599
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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- Create/update Centaur chips, MBS, MBA units
- Add unit testcase to query the Centaurs
- Update the Venice, VBU target instances
- Increase max endpoint pairs to 10
- Other general model updates for compatibility, consistency
- Register FSISCOM and SCOM operations with DD framework for Centaur chips
Change-Id: If43bc57888e66b7d2ea53704ca703328eec844f9
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/465
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Change-Id: Ia65187cd475da725250a17cec59b1aa6ff805f84
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/453
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Tested-by: Jenkins Server
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