| Commit message (Collapse) | Author | Age | Files | Lines |
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- In MPIPL the HW interrupt config could be such that interrupts will
cross node boundaries. HB handles interrupts independently on each
node - so initialize INTRP in a way to handle this transition.
- Modify the MPIPL flow with the following changes:
a) Set the Interrupt LSI State Machine to disabled
b) Enable LSI Mode via the Interrupt Control Register
c) Force all nodes to sync after steps a + b
- Enable INTRP Multi-Node MPIPL Sync Code developed in P8
- Each node will now initialize its own internode_info
data area during an initial IPL
- Coalescing of the Host will modify this data to define
all the nodes in the system
- During the MPIPL each node can view each others area to
determine when all nodes have reached the common sync point
- Remove Legacy P8 MPIPL INTRP Code that is not used
Change-Id: Idb742eafc7389f328ea7f506c4c4541c989e52b6
RTC: 182712
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57993
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Richard J. Knight <rjknight@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Ran into a case where Hostboot was getting booted with the wrong
fabricid for the node it was on. In the process I realized it
was hard to tell what was going on.
Added printk output to show the PIR of the boot core.
Modified how force-hrmor option is consumed in ecmd-debug-framework
so that you can force unnatural lookups.
Change-Id: I77fc614889aa3cedcc8ccd39cac9ebc36f239b56
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57910
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-by: Roland Veloz <rveloz@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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When Hostboot has a TI with a PLID rather than a Reason Code (RC), HWSV does not
attempt the Hostboot Dump. Thought is that happens per the design as the error
log related to the PLID sent by Hostboot should already have the required
information. There are instances where the error log does not have sufficient
data and a dump would be beneficial. A path is being added so an error log can
be flagged as needing a Hostboot dump.
Change-Id: I97972308c70e7210f578fb818563bb9b0cd940b4
CQ: SW420219
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56600
CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com>
CI-Ready: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Corey V. Swenson <cswenson@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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PHYP needs a way to know if SBE security backdoor is enabled
for debug purposes. This change creates a flag in TPM instance
data structure to indicate whether the backdoor is enabled. This
flag is passed by SBE to the hb bootloader; also added the flag
to indicate whether PCR is poisoned (default of 0).
The population of this flag will be implemented on Fleetwood.
Change-Id: I22305dbc9651134ba7dfe3b0bd3c760fe53c2c85
RTC: 188961
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56045
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com>
CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Default MSR[ME]=0 during initial boot for bootloader and
hostboot kernel
Once the xscom address range has been mapped in, enable the
machine check handler to force a checkstop and set MSR[ME]=1
to allow regular machine check handling
CQ: SW401402
Change-Id: I104e39465e61b3b19d5c073e71271102711ae54f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47179
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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- Addresses review comments from original commit
- Adds inband scom multicast workaround
Change-Id: Ia17a8e5359227691464f3552ded585ede771813b
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55305
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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- Add function to compress SCOM address
- Old MCS target is now DMI
- Add istep12 call to enable inband SCOMs
- Set each DMI offset attribute in processMrw
Change-Id: If5171f8da6c58404ac598047ca0177aead048771
RTC:147272
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54574
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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- Display size of page requested if requested memory
doesn't become available
Change-Id: I5b101ce6650cdc155be276c5d00f95bc35a0ff90
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54491
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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P9 Doorbells operate differently than P8 IPI mechanism, creating
a race condition. Basically because the HB kernel turns a
doorbell into a message, and then is ready for another one -- it
can lose the next one since repeated messages with same key are
dropped (IPC handling clears memory comm area, other HB instances
notice, fill and drop a doorbell before getting back into kernel)
Change-Id: I8eb6f010600afb9de365c8942fcd24227903436f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54118
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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-Fixed node/group id calculations
-Reduced dbell printk to prevent printk overflow
-Fixed architectual hole in how internode IPC works
Workitems won't work, instead just always check
for IPC on any doorbells to master thread
-Changed PIR tracing to print out in hex
Change-Id: I25eb7f87fd812a90f98a7724b1ac1100f764fe7b
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53187
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
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- move p9_fab_iovalid to fab_iovalid common lib
to avoid conflicts with hwp lib
- doorbell_send to wake up the cores in istep18
- move block wakeup interrupts set later in the
istep 18 flow after we have suspended the mbox
and drained the interrupt queue
Change-Id: I241240ca1d1787182c5baaf3bdd10283878d5798
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52701
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: SWATHI M. BHATTIPROLU <bhmadhur@in.ibm.com>
Reviewed-by: Sakethan R. Kotta <sakkotta@in.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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- Use doorbells instead of IPIs (no IPI support
using LSI interupts in the XIVE intr architecture)
- New message type from kernel to userspace so the
kernel can notify the HB userspace Interrupt
Resource Provider (INTRP) that an IPC message was
sent to the particular HB instance (in P8 this
happened automatically as that was part of the
IPI architecture).
- Re-enable testcase that validates that an IPC
message can be successfully sent.
Change-Id: Ic846f8dca45217205ed61d8381a573e995cb16f2
RTC: 150861
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52004
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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We hit out-of-memory errors while trying to boot a Opal system
due to the large amount of memory used by the PM procedures
and the pinning of memory in secure mode.
Also did some other rearranging of the pinned memory sections
to get some space back.
Change-Id: I61f219d7f32871a39b236d963bae893a6ef0ce0e
CQ: SW413191
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51724
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Change-Id: Iadfded90c09b149948348ee462ab34f9c2431982
RTC: 182134
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49865
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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during istep 15/16 of HCODE build/execution
Change-Id: I63f54cdc35b3ff7e68120a07c142b6a557257854
RTC: 180760
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49070
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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- Extends hostboot memory from 32 to 48 MB to handle large code loads
- Dump 48 MB in hostboot dump script
- Support 48 MB hostboot size in debug framework
Change-Id: I3e64e85a7e2455bc4add2f2db9b48f57db433c7d
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43735
Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com>
Reviewed-by: Stephen M. Cprek <smcprek@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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At this time we are trying to secure OpenPOWER in secure mode,
but allow best effort policies in other scenarios
Change-Id: I9ec2b5be49dbfcff678c4d30bb85f8762e448cb6
RTC: 170136
RTC: 155374
RTC: 168021
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43640
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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RTC: 165369
Change-Id: If15f6ccc7a7c3649b8352467ae10173a15f3f501
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44426
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Previously two bits were covering SLB type machine checks. One
of those bits now represents cresp load machine checks. This
commit makes it so that cresp load machine checks no longer
go down the SLB handling path. Also adds in some more printks
for the next developer.
RTC: 156832
Change-Id: I3e03601f20b85dc9dec9c5fc2319c28472c03240
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43354
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Change-Id: I9ec35ca8dd513a5e31f69cd899fa5d1e00d41c63
RTC: 175114
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42442
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Relocate Page Manager Page Table to 256K alignment after preserved area
Simplify page manager initialize
Change-Id: Ic90584437fa68843a7ebe3818d48c3fe4f5157d8
RTC: 175114
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42154
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Change-Id: I3e870c9b50d13704c4c88adfc96e5943cff9dae2
RTC: 175114
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42153
Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Remove hacks to set LPC and XSCOM MMIO BAR default values in Bootloader and in
data passed to Hostboot (defect SW391259).
Change-Id: I3df6accadda8a5c461d969ed38e7970bc37291c9
CQ: SW391539
CMVC-Prereq: 1026637
Depends-on: I55ca10034d7adf3e766edb4d0071f649c7c90446
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41556
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Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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This is a further fix that was missed in 10983d35f568 ("Convert cmpi to
cmpwi to fix build for modern binutils").
In the past binutils would assume 'cmp' meant 'cmpw'. Modern binutils
require the explict use of cmpw or cmpd.
The first two instances are dealing with SPRs, which are 32-bit, so cmpw
is correct.
It is not clear what to do in the third use of cmp, but given old toolchains
have generated cmpw lets assume that we should maintain the behaviour.
Change-Id: Iee5dd5903dcd7ac4028bab0176e08ce3db23b2d5
Signed-off-by: Joel Stanley <joel.stanley@au1.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42476
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Currently the BlToHbData structure asserts when a caller asks for
info, but the structure was initialized as invalid. Now for the
the fields that have valid default values, we allow access to them.
Change-Id: I703526ab30c47c0e7723dbbfaf876ce4e2da6e3a
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42321
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Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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From Linux 80f23935cadb ("powerpc: Convert cmp to cmpd in idle enter sequence"):
PowerPC's "cmp" instruction has four operands. Normally people write
"cmpw" or "cmpd" for the second cmp operand 0 or 1. But, frequently
people forget, and write "cmp" with just three operands.
With older binutils this is silently accepted as if this was "cmpw",
while often "cmpd" is wanted. With newer binutils GAS will complain
about this for 64-bit code. For 32-bit code it still silently assumes
"cmpw" is what is meant.
In this instance the code comes directly from ISA v2.07, including the
cmp, but cmpd is correct. Backport to stable so that new toolchains can
build old kernels.
This is change is a noop with the existing toolchain. We change from
implicitly generating the cmpwi to explicitly stating in for
compatibility with newer toolchains.
With gcc 4.9.3, binutils 2.25.2:
$ cat asm-test.S
.text
.global test
cmpi 0, 8, 1
$ powerpc64-linux-gcc -c asm-test.S
$ objdump -d asm-test.o
0000000000000000 <.text>:
2c 08 00 01 cmpwi r8,1
Old compiler, updated instruction:
$ cat asm-test.S
.text
.global test
cmpwi 0, 8, 1
$ powerpc64-linux-gcc -c asm-test.S
$ objdump -d asm-test.o
0000000000000000 <.text>:
2c 08 00 01 cmpwi r8,1
And then the new toolchain (gcc 6.3.0, binutils 2.28) with the updated
asm:
$ cat asm-test.S
.text
.global test
cmpwi 0, 8, 1
$ powerpc64-linux-gnu-gcc -c asm-test.S
$ objdump -d asm-test.o
0000000000000000 <.text>:
2c 08 00 01 cmpwi r8,1
Change-Id: If981e20a578ec98ede68a31eee2888c27d5c3d10
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42259
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Reviewed-by: STEWART E. SMITH <stewart@linux.vnet.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Change-Id: Iaf7ae4b48da327f89c29c8b394de4dad3c3ec7f2
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42303
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
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Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
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Reviewed-by: Matthew A. Ploetz <maploetz@us.ibm.com>
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This commit fixes an issue where data was incorrectly added to the
middle of the existing BlToHbData struct. The secure settings
at fault have been moved to the end of the structure.
Change-Id: I9ecb3256325aaeb633e250cb60e4f4ffc6010dba
RTC:163094
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42005
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Stephen M. Cprek <smcprek@us.ibm.com>
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Change-Id: Ic9b220dc3480c13e1b1ac1c69a0be148ab5ea977
RTC:163094
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41114
Reviewed-by: Stephen M. Cprek <smcprek@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
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Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Temporarily disable use of MMIO BAR remapping
Change-Id: Idc01a4f05834a8d6c07fce40850846028d9f8f47
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41463
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If the master processor has no memory behind it the entire
memory map must be modified. Each processor has its own statically
defined map that covers both memory and MMIOs. If the master
has no memory, its memory map is swapped with another processor.
Each processor gets a new effective fabric id that is then used
to compute all of the BAR values for those processors.
The SBE boots with a certain memory map programmed into the master
processor. That value is then passed up through the bootloader
into Hostboot. This value is compared to the BAR values that
Hostboot assumes it is using. Based on that comparison, various
attributes are computed to match the effective fabric positions.
Change-Id: I2b0d1959c303df8c9c28c8f0a5b5be1e77aa154f
RTC: 173528
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40359
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Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
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Also added entries for
-kernel startup
-cxx testcase start (99.1)
-shutdown
Change-Id: I870961ae8ea0b43003db6bafb21addf660ab99ef
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40346
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The termWritePLID function is not used by Bootloader, so does not
need to be included in the image.
Change-Id: I0df52e012f14352745d3aead1ca90fe83fe7a9d4
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40289
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Reviewed-by: Corey V. Swenson <cswenson@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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GCC6 throws the following error:
operand type ?bool*? is incompatible with argument 1
of ?__sync_fetch_and_and?
GCC documents that bool is invalid for __sync builtins over at
https://gcc.gnu.org/onlinedocs/gcc/
_005f_005fsync-Builtins.html#g_t_005f_005fsync-Builtins
"GCC allows any scalar type that is 1, 2, 4 or 8 bytes in size other
than the C type _Bool or the C++ type bool"
Change-Id: I4608b03e5d8aa16a0a350030b552a8f8e791649c
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36898
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Reviewed-by: Richard J. Knight <rjknight@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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Added check for bit 18 to distinguish between Nimbus DD1.0 and
Cumulus DD1.0
Consolidated Nimbus DD1 checking to a common function
Added printk output that shows which CPU we're running on
Modified some existing printk output to use fewer characters
Change-Id: I1c42df0051fc2d9cc5fa54d95f68c3bd26b86462
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39876
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Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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- Include a generic error pipleline for other future error
scenarios to leverage this functionality
Change-Id: Icc1399ee93157c7106d394944a3355285a8cd830
RTC: 171865
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39072
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Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Add support to BlToHbData structure and create new version.
Put in TODOs for pending p9_sbe_hb_structures.H changes.
Move selected Bootloader data out of image due to size issues.
Update BlTrace tool for new location of trace data.
Change-Id: Ic513a95b8f4054d467537c4623d5a7b7aa09e25e
RTC:173526
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Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Previously this register only had 2 values. "running" in ascii and 0
This commit adds 3 more possible states. Now 0 represents that HB
passed off control to the hypervisor. "shutdown" represents that HB
TI'ed. "bootload" says we are in the bootloader. "starthbb" means
the bootloader has started the base image. "running" means hostboot
is up and running.
Change-Id: I11e7ef3dbb559a221343070b2c1b15f67853710b
RTC: 171742
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39730
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Also add ErrnoToString() as a test which is a functionality
ported from p8
Change-Id: Ia6dd9b37638af2634267e224d9b97133bf984fb4
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38956
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-Add validation to heap allocations, marker
used to detect buffer overruns to generate
exception when memory segment is freed
-Add additional debug to the heap bookkeeping
data - owner tid, reserved size and an
indicator to say it is an allocated chunk
Change-Id: Iae522fc4c6157a32f5689ee1ec5fd9d552123eb4
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Disable verification in bootloader if SAB not set
Change-Id: If5f1adcbe0277f2a4223d8cea6a5e2048019871d
RTC: 167741
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37214
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Create Bootloader to hostboot data manager to control how
the shared data is accessed and modified.
Change-Id: I54cb543ed289810ab6afb07d333313f5662bce0e
RTC: 166848
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35617
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Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Created new PVR_t structure that understands how to decode the
PVR for Nimbus DD1 and future versions.
Change-Id: Ie7e6f62d65fb1a3e11b1021f1600e7421b8c30a9
RTC: 160361
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37303
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Reviewed-by: Matthew A. Ploetz <maploetz@us.ibm.com>
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- Latest HCODE image change requirements
now need to enable LPCR[17] prior to issuing STOP
Change-Id: I21488e0795b5dcd710b026ebbace2d158fdf9694
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Adding some @error tags for the critical kernel TIs so that
a description ends up getting into Knowledge Center.
ForwardPort: yes
Change-Id: Ibe468d25a9390ab5f4285d969b9e9c838830f216
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34792
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As a first step to providing Bootloader error handling add support
for a terminate function.
Change-Id: Id4f8f130376d1396cd4feb796d1a3a908558225b
RTC:135746
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Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Corey V. Swenson <cswenson@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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I have had to look this up 1 too many times, I think adding this
comment here will help me and whoever hits this in the future
Change-Id: Ib434d2d56a90770cbdd45b1e52f0bea5fdc62158
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31905
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Matt Derksen <v2cibmd@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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Remove all of the old fapi1 HWPs from P8
Update makefiles/code to not include old hwpf headers
Change-Id: Idc840554721f68b0af3b6ee6c7ad84f5df258e60
RTC: 146345
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28844
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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P9 moves us from 8 scratch registers to 4. This commit handles
this change and also adds the base support for partial cache.
Change-Id: Ibe050c663744285dd3e77850649236a669dadbd6
RTC: 150923
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27462
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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Check scom register (0x1001181B) for reduced cache mode and expand the
memory footprint appropriately, reduced 8MB or full 10MB.
Change-Id: I5920572077cdcee317e7b3b9abe999e6de295459
RTC:152954
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27522
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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