summaryrefslogtreecommitdiffstats
path: root/src/include/usr/lpc/lpcif.H
Commit message (Collapse)AuthorAgeFilesLines
* Add support for LPC error detection and recoveryBill Hoffa2017-09-181-1/+2
| | | | | | | | | | | | | | | Change-Id: Iea9bd4425aeb798acd85484402c627fb623cae94 Also-By: Matt Ploetz <maploetz@us.ibm.com> RTC: 133649 RTC: 134582 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45397 Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Map BAR attributes based on data from BootloaderDan Crowell2017-06-021-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | If the master processor has no memory behind it the entire memory map must be modified. Each processor has its own statically defined map that covers both memory and MMIOs. If the master has no memory, its memory map is swapped with another processor. Each processor gets a new effective fabric id that is then used to compute all of the BAR values for those processors. The SBE boots with a certain memory map programmed into the master processor. That value is then passed up through the bootloader into Hostboot. This value is compared to the BAR values that Hostboot assumes it is using. Based on that comparison, various attributes are computed to match the effective fabric positions. Change-Id: I2b0d1959c303df8c9c28c8f0a5b5be1e77aa154f RTC: 173528 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40359 Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
* pnor: Add AST Mailbox protocol supportBenjamin Herrenschmidt2017-05-011-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a new alternative PnorDD that uses the Asped AST Mbox protocol as supported by OpenBMC. To enable this, you need these changes to the config: @@ -1,10 +1,12 @@ -# The Serial Flash Controller is the AST2400 BMC. -set SFC_IS_AST2500 +# We use BMC MBOX protocol for flash accesses +set PNORDD_IS_BMCMBOX +unset PNORDD_IS_SFC +unset SFC_IS_AST2500 unset SFC_IS_AST2400 unset BMC_DOES_SFC_INIT unset SFC_IS_IBM_DPSS -set ALLOW_MICRON_PNOR -set ALLOW_MACRONIX_PNOR +unset ALLOW_MICRON_PNOR +unset ALLOW_MACRONIX_PNOR Other systems need to set PNORDD_IS_SFC Change-Id: I8901288c98d8d0fce8c9a0fb31267f0001b2a731 Not-yet-signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> RTC: 170096 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39387 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Matthew A. Ploetz <maploetz@us.ibm.com>
* XSCOM/LPC Workaround for Nimbus DD1Dan Crowell2017-02-161-1/+8
| | | | | | | | | | | | | | | | | | There is a shared resource between the XSCOM and LPC logic that leads to errors at the XSCOM level causing errors to be detected during LPC operations. This commit adds an external interface to access block LPC operations while an XSCOM operation is in flight. Change-Id: I571094dfb666aa9198fabec5280a0f45c62c90ba RTC: 167291 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36399 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Split out SFC logic and add support for AST2400Dan Crowell2014-10-141-4/+4
| | | | | | | | | | | | | | | | Refactored the PNOR device driver to pull all SFC-specific code into a new set of classes. Any time a new type of serial flash controller (SFC) is introduced, a new subclass should be created to support it. Also added the full support for the AST2400 BMC that is being used on Palmetto. Change-Id: I9cdbf9b48bbf94615a39804920e170a3142ec386 Origin: Google Shared Technology RTC: 97493 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/13229 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Create LPC Device DriverDan Crowell2014-09-221-0/+64
Split LPC function out from PNOR DD and incorporate Stradale changes Change-Id: I4162db1a9f52ba3c0c973438b7b70baeae00aee2 Origin: Google Shared Technology RTC: 97494 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/11198 Tested-by: Jenkins Server Reviewed-by: Michael Baiocchi <baiocchi@us.ibm.com> Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
OpenPOWER on IntegriCloud