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* Base targeting support for Axone memory complexChristian Geddes2018-08-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Added 3 new target types to start things off. These are the OMI (open-capi memory interface), the OMIC (open-capi memory interface controller), and the MCC (memory channel controller). These new targets will help us represent the new memory complex we are using for axone. The axone memory hiearchy will look like this: MI--MCC / \ Proc--MC < __ OMI--OCMB--MEMPORT--DIMM \ / OMIC **Note that OCMB/MEMPORT have not been implemented in hostboot yet Change-Id: I3df4eb3e279f825f0bdee86448ea23cb975e5511 RTC:172969 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63744 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: ILYA SMIRNOV <ismirno@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
* Adding FSI and PNOR interfaces for PRD FIRDATA in HBRTElizabeth Liner2017-02-161-1/+5
| | | | | | | | | | Change-Id: I515a328e50536d92f0ab80229cd8d939f89412c7 RTC:127358 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35008 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Include MFSI offset for Centaur access from OCCDan Crowell2015-10-061-1/+1
| | | | | | | | | | | | | | | | | Add the FSI offset for the MFSI master to the base address for cascaded slaves, this allows access to the Centaurs hanging off the non-master processors from the OCC FIR collection code. Change-Id: I5b6c1d77e90f233cab99bb74f5374d0456093cbc CQ: SW322919 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/20930 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Zane Shelley <zshelle@us.ibm.com> Reviewed-by: MATTHEW A. PLOETZ <maploetz@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* New interfaces to get FSI and PNOR info for Xstop codeDan Crowell2015-02-181-2/+5
| | | | | | | | | | | | | | | Added new external interfaces to retrieve information about the FSI topology and the PNOR characteristics in order to enable the checkstop analysis code that runs on the OCC. RTC: 108820 Change-Id: Ibbe9bca8eee4c8ac86006b1ad881bd8b2c3b8280 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/15726 Tested-by: Jenkins Server Reviewed-by: Zane Shelley <zshelle@us.ibm.com> Reviewed-by: William H. Schwartz <whs@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* BMC: VPD Caching in PNORCorey Swenson2014-10-171-1/+3
| | | | | | | | | | | | | For MVPD CVPD SPD, during presence detect VPD part number and serial number are compared between PNOR and SEEPROM. Mismatch triggers copy of VPD from SEEPROM to PNOR. Change-Id: Ia0a7b3fdf80bc15aee05c1303efa406fffa318ce RTC: 106885 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/13233 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Reset all slaves during initial FSI setupDan Crowell2014-06-201-0/+2
| | | | | | | | | Change-Id: I9652e3ef727e022e3462fb92d93d9569f7d0ee41 CQ: SW260037 Backport: release-fips811 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/11072 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Change copyright prolog for all files to Apache.Patrick Williams2014-05-212-20/+20
| | | | | | | Change-Id: I5664587b4f889099290ef50d50fa9ce5e580e1eb Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/11167 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Set CMFSI fields correctly in the devtree for altmasterDan Crowell2014-05-211-0/+26
| | | | | | | | Change-Id: I4a36c70d36ec0603d053d5198a2aa78c07c63334 RTC: 35041 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/10626 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* FSI support for alt-masterDan Crowell2014-04-251-2/+3
| | | | | | | | | | Change-Id: I131ef80db728bde1218d6691219159b765a9c4d9 RTC: 35041 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/10043 Tested-by: Jenkins Server Reviewed-by: Michael Baiocchi <baiocchi@us.ibm.com> Reviewed-by: Corey V. Swenson <cswenson@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Fix FSI MRW ParsingDan Crowell2014-04-151-1/+3
| | | | | | | | | | | | Missed a case where the alt-master chip was pointing to the wrong master. Change-Id: I0e8010c5adb871344a7d1fd11fefd7f7f152ec72 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/10529 Reviewed-by: Andrew J. Geissler <andrewg@us.ibm.com> Tested-by: Jenkins Server Reviewed-by: Michael Baiocchi <baiocchi@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Improved handling for bad scom/fsi failuresDan Crowell2014-04-031-0/+7
| | | | | | | | | | | | | | | | Added more error recovery to the FSI logic to handle cases where a bad scom would leave the hardware in an error state for the next IPL. See SW252028 for details on the failing scenario that exposed the problem. CQ: SW253637 Backport: release-fips810 Change-Id: I37c5625414247c7a65c4b1a7d631c6764c3606fc Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/9840 Tested-by: Jenkins Server Reviewed-by: Michael Baiocchi <baiocchi@us.ibm.com> Reviewed-by: Corey V. Swenson <cswenson@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Improve FSI PIB2OPB Error RecoveryDan Crowell2014-03-031-2/+12
| | | | | | | | | | | | Modified which error bits are checked in the PIB2OPB status as well as changing a few error reset functions. Change-Id: I27676947983f0b66c940d68bbd5f134912749ad9 CQ: SW248395 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/9238 Tested-by: Jenkins Server Reviewed-by: Michael Baiocchi <baiocchi@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* FSI Error HandlingDan Crowell2013-10-172-4/+17
| | | | | | | | Change-Id: Ie4d9b8d96fd84b4b263466c7637e5e9ef2641f50 RTC: 35287 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/6442 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* FSI SCOM Error HandlingDan Crowell2013-09-132-2/+6
| | | | | | | | Change-Id: I1538fbf386d5480e473f3f0b049492d494412624 RTC: 35064 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/5825 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* HB-driven FSI Init (part 1)Dan Crowell2013-08-231-1/+2
| | | | | | | | | | | | | | | With this code an IPL on a single DCM system makes it up into cen_sbe_tp_chiplet_init1 before it fails due to a Centaur SBE issue. In addition to changes in the init flow, some updates have been made to the error recovery/logging paths. Similar results now seen on 2-DCM system. Change-Id: I6c4b31ee568919c81d388c99ceb26c24705da9be RTC: 67844 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/5394 Tested-by: Jenkins Server Reviewed-by: William H. Schwartz <whs@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Add FSI FFDC Data CollectionMike Baiocchi2013-05-152-23/+47
| | | | | | | | | | | | | | To address the request to update present detect error log, we've added getFsiFFDC() and related functions. We've called these functions in the fail paths of the present detect functions. Change-Id: I763bf4056c35ebebdf7a0f2d4d3d31862a4d0091 RTC: 66865 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/4116 Reviewed-by: Michael Baiocchi <baiocchi@us.ibm.com> Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Add FSI Registers to FFDC section in FSI device driverMike Baiocchi2013-02-281-24/+24
| | | | | | | | | | | | | | Added error log user detail sections into several error paths of FSI deveice driver functions. These sections added targets and registers to the error log. Change-Id: I37622381ab0dd48454a9810233cdb11d725c5ed6 RTC: 44490 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/3305 Tested-by: Jenkins Server Reviewed-by: ADAM R. MUHLE <armuhle@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Use VPD to verify FSI presence detectDan Crowell2012-07-111-23/+26
| | | | | | | | | | | | Changing the presence detect logic for the chips to look at VPD in addition to the FSI presence. Creates errors if they don't agree, except in VPO where FSI presence detection is busted. Change-Id: I17246413abad5c8cb78a9166606f666bb860c081 RTC: 44075 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1277 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Use remote xscom for remote centaur FSI opsDan Crowell2011-12-081-1/+7
| | | | | | | | | | | | | | | | | | | | Task 4086 If the powerbus is alive we will use the remote master's OPB logic directly instead of using the master proc's logic and cascading through the MFSI port. Added a target-specific mutex to handle concurrency issues. Note - the new code path cannot be tested until XSCOM is completed with Story 4382 I also modified some error handling to take care of errors exposed by the fsipres testcase. Verified on SALERNO and 2-proc VENICE models. Change-Id: If48ddde60cef819ff6b921e00bdbab5027830be4 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/569 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* FSI Presence Detect for Proc and MemBufPatrick Williams2011-12-061-2/+3
| | | | | | | | | | Change-Id: I282a764fbfb81cf13cc9d41ee275bafff478d20e Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/519 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: ADAM R. MUHLE <armuhle@us.ibm.com> Reviewed-by: Terry J. Opie <opiet@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Adding support for remote FSI accessesDan Crowell2011-10-271-0/+22
| | | | | | | | | | | | | | | | | RTC Story 3792 - Added 7 more Venice targets and 7 more Centaur targets to the simics_VENICE.system.xml to match the latest simics config Note: remove Centaurs are currently disabled due to SW107421 - Modified testcases to be more tolerant of system config differences - Changes to initialization flow to be more tolerant of missing chips - Expanded the size of the HB_DATA section of PNOR to hold the additional targets (up to 128KB space now, actual is 36KB) Change-Id: Ic92708ccb147fb18bf992ef3ac318a287d32fafe Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/445 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Pull FSI data from real attributes (Task 3909).Dan Crowell2011-10-142-30/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | There are a group of attributes defined for FSI now. -ATTR_FSI_MASTER_CHIP -ATTR_FSI_MASTER_TYPE -ATTR_FSI_MASTER_PORT -ATTR_FSI_SLAVE_CASCADE -ATTR_FSI_OPTION_FLAGS Also includes work for Story 3996. The attributes are now broken into 3 distinct pieces: - attribute_types.xml : defines hostboot attributes - target_types.xml : defines different types of targets - XXX.system.xml : system-specific information, equivalent to what we'll get from system workbook These are then used to generic system-specific binaries, currently for 3 platforms: - simics_SALERNO_targeting.bin - simics_VENICE_targeting.bin - vbu_targeting.bin Change-Id: I2bf920cc62cceb761ab44a07df433da44249d0e0 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/426 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Initialize the FSI hardware - Story 3551Dan Crowell2011-10-052-3/+81
| | | | | | | | | | | | | | | | | | | | | | This code will initialize the FSI hardware and allow access to remote slaves. Note - current code is hardcoded to using the MFSI-0 port on the master processor wrapped back into its own CFAM. Note2 - One testcase is disabled pending integration of required fixes to the simics models. Contains work for - Task 3830 : FSI Master Regs - Task 3831 : FSI Slave Regs Change-Id: I8dd5f0e03cf083e35cf8241db22ad6d76ba85fac Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/359 Tested-by: Jenkins Server Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: ADAM R. MUHLE <armuhle@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Implementing FSI driverDan Crowell2011-09-061-0/+51
-Initial work for FSI Device Driver (Story 3334) -Read/Write interface (Story 3550) Code is capable of basic read and write operations provided that the Simics models are updated Note: contains early work for FSI Initialization that should be ignored for now Change-Id: I08e795422de127b62c2d1629d7a4e0f12b21e348 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/287 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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