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* Add retry to slave core wakeup pathDan Crowell2019-01-251-1/+17
| | | | | | | | | | | | | | | | | | | | We are still seeing some very intermittent errors in the slave core wakeup path. It still seems like we may have a timing issue. Until we figure out exactly what is going on, I am adding a retry mechanism that should get the core to report in correctly. The retry is done by issuing an additional doorbell message to the core that didn't report in. Change-Id: Ib87e5d58e079674d1eebb44c10d0252a35ea0519 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70761 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Inband MMIO access to OCMBRick Ward2018-12-131-1/+14
| | | | | | | | | | | | | | | | | | This is an untested version of the new MMIO device driver that will give access to the OCMB. It will be tested once the Axone model IPLs in Simics. Change-Id: I4bc1d2f7306f1b238d1d65c24462ac4121266b11 RTC: 189447 RTC: 189220 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66941 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Matt Derksen <mderkse1@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* PRD: Make room for Axone prf files in HostbootZane Shelley2018-11-161-2/+2
| | | | | | | | | | | | | Change-Id: Ic0f4fda42326f714538b392c4599398d9dfc65e5 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68811 Reviewed-by: Brian J. Stegmiller <bjs@us.ibm.com> Reviewed-by: Caleb N. Palmer <cnpalmer@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
* PRD: Make room for Axone prf files in HBRTZane Shelley2018-10-311-2/+2
| | | | | | | | | | | | | Change-Id: Id4c742e1fd9d7925d5ee8a7451893e27c5501a4f Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68168 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Caleb N. Palmer <cnpalmer@us.ibm.com> Reviewed-by: Brian J. Stegmiller <bjs@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
* Added support for recursive mutexesMatt Raybuck2018-10-291-8/+56
| | | | | | | | | | | | | | | | There was only support for non-recursive mutexes. This commit adds support for recursive mutexes and a new API for using them. Change-Id: I664c181af1633b05b8b2da6b1ff21b93a37cec28 RTC: 196793 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67938 Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Ilya Smirnov <ismirno@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Base Core/Kernel Changes to Support the Axone Processor ChipBill Hoffa2018-08-201-0/+2
| | | | | | | | | | | | | | | - Add the new cpu type, update the pvr checks and other miscellaneous changes to support a new Axone proc chip type Change-Id: Ie2541bf826bdff65f6f11b0f16839855d69eb4d6 RTC: 173001 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64260 Reviewed-by: Matt Derksen <mderkse1@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Add Get Nodal HRMOR UtilityBill Hoffa2018-07-071-0/+11
| | | | | | | | | | | | | Change-Id: Iebd302b7fb33b56c1bc3ea070b25d437134ea523 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61592 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61808
* Fixes to node IPC messaging to handle non-zero base addressesBrian Bakke2018-06-073-3/+36
| | | | | | | | | | | | | | | | | | | | Current code has each Node calculate each Remote Node's IPC area remote address by performing a fixed format calculation. This change has each Node calculating its IPC area Remote address and posting this value to a local SCOM register. A Node reads a Remote Node's SCOM register to acquire the Remote IPC area address. Change-Id: I25260ce180e0d07e5e81990d4c1f99e249912491 RTC:191463 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59177 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Implement Interrupt Resource Provider Init for MPIPL Multi-Node SystemsBill Hoffa2018-05-071-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - In MPIPL the HW interrupt config could be such that interrupts will cross node boundaries. HB handles interrupts independently on each node - so initialize INTRP in a way to handle this transition. - Modify the MPIPL flow with the following changes: a) Set the Interrupt LSI State Machine to disabled b) Enable LSI Mode via the Interrupt Control Register c) Force all nodes to sync after steps a + b - Enable INTRP Multi-Node MPIPL Sync Code developed in P8 - Each node will now initialize its own internode_info data area during an initial IPL - Coalescing of the Host will modify this data to define all the nodes in the system - During the MPIPL each node can view each others area to determine when all nodes have reached the common sync point - Remove Legacy P8 MPIPL INTRP Code that is not used Change-Id: Idb742eafc7389f328ea7f506c4c4541c989e52b6 RTC: 182712 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57993 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Richard J. Knight <rjknight@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Force checkstops for unhandled machine checksDan Crowell2018-03-291-1/+11
| | | | | | | | | | | | | | | | | | | Default MSR[ME]=0 during initial boot for bootloader and hostboot kernel Once the xscom address range has been mapped in, enable the machine check handler to force a checkstop and set MSR[ME]=1 to allow regular machine check handling CQ: SW401402 Change-Id: I104e39465e61b3b19d5c073e71271102711ae54f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47179 Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Inband SCOM clean upCorey Swenson2018-03-201-2/+4
| | | | | | | | | | | | | | | - Addresses review comments from original commit - Adds inband scom multicast workaround Change-Id: Ia17a8e5359227691464f3552ded585ede771813b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55305 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
* Changes to Inband SCOM MMIO ranges for CumulusCorey Swenson2018-03-081-4/+4
| | | | | | | | | | | | | | | | | | - Add function to compress SCOM address - Old MCS target is now DMI - Add istep12 call to enable inband SCOMs - Set each DMI offset attribute in processMrw Change-Id: If5171f8da6c58404ac598047ca0177aead048771 RTC:147272 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54574 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
* Multi-Drawer (IPC) Interrupt/Messaging SupportBill Hoffa2018-01-251-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | - Use doorbells instead of IPIs (no IPI support using LSI interupts in the XIVE intr architecture) - New message type from kernel to userspace so the kernel can notify the HB userspace Interrupt Resource Provider (INTRP) that an IPC message was sent to the particular HB instance (in P8 this happened automatically as that was part of the IPI architecture). - Re-enable testcase that validates that an IPC message can be successfully sent. Change-Id: Ic846f8dca45217205ed61d8381a573e995cb16f2 RTC: 150861 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52004 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Enable ATTN prior to OPAL handoffBrian Bakke2017-11-301-0/+7
| | | | | | | | | | | | | Change-Id: Iadfded90c09b149948348ee462ab34f9c2431982 RTC: 182134 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49865 Reviewed-by: Matt Derksen <mderkse1@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Story 180760 - Use self restore API to disable ATTN in HID ...Brian Bakke2017-11-071-0/+1
| | | | | | | | | | | | | | | during istep 15/16 of HCODE build/execution Change-Id: I63f54cdc35b3ff7e68120a07c142b6a557257854 RTC: 180760 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49070 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Matt Derksen <mderkse1@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
* Ensure AbaPtr is not used in runtime codeDan Crowell2017-10-191-1/+4
| | | | | | | | | | | | | | | | | The AbaPtr makes assumptions that we have pointer values that are only 32-bits long. In our runtime (HBRT) environment that assumption is not true so we need to make sure none of the code that runs there is trying to use the AbaPtr code. Change-Id: I0a26558f305fada723bf3cb3447a2bdfddb194d0 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48248 Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Matt Derksen <mderkse1@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Remove half cache init and do it in the page managerStephen Cprek2017-07-201-2/+1
| | | | | | | | | | | | | Change-Id: I3e870c9b50d13704c4c88adfc96e5943cff9dae2 RTC: 175114 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42153 Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Fix PVR check for Nimbus DD1Dan Crowell2017-05-111-0/+6
| | | | | | | | | | | | | | | | | | Added check for bit 18 to distinguish between Nimbus DD1.0 and Cumulus DD1.0 Consolidated Nimbus DD1 checking to a common function Added printk output that shows which CPU we're running on Modified some existing printk output to use fewer characters Change-Id: I1c42df0051fc2d9cc5fa54d95f68c3bd26b86462 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39876 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Corey V. Swenson <cswenson@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Include HUID of failed Proc in TI data for certain SBE errorsBill Hoffa2017-05-101-1/+3
| | | | | | | | | | | | | | | - Include a generic error pipleline for other future error scenarios to leverage this functionality Change-Id: Icc1399ee93157c7106d394944a3355285a8cd830 RTC: 171865 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39072 Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Port P8 HBI page verification functionalityStephen Cprek2017-05-011-1/+6
| | | | | | | | | | | | | | Verify HBI pages via its securely signed hash page table Change-Id: I86d29ee393c19aa0d9c5270b0b6c561a9fc4ab51 RTC: 167668 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39071 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
* Remove devtree codeDan Crowell2017-04-261-3/+2
| | | | | | | | | | | | | | OPAL is now HDAT-based, removing all references to the Hostboot-generated devtree. Change-Id: I9fc8773f7135d4e0d4799e4cc7c6e3b6ea1da14d Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39293 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com> Reviewed-by: Matthew A. Ploetz <maploetz@us.ibm.com>
* Fix OCC Host Data OffsetCorey Swenson2016-10-051-7/+5
| | | | | | | | Change-Id: I1e23ebe452049d86bfd1b1fdafd14f5e48309fb2 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30687 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Implement XIP Customization for Core InformationMarty Gloff2016-09-071-1/+1
| | | | | | | | | | | | | | | | | Loop to run xip_customize on the pnor image for each core must still be implemented. This commit also enables the call of p9_xip_customize only when not in the FSP environment. Change-Id: Iafc04e2ba05def7794315f9178b55dd2f2de35e4 RTC:158044 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28098 Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Matt Derksen <v2cibmd@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Updates for new scratch registers in P9Andrew Geissler2016-08-161-18/+8
| | | | | | | | | | | | | | | P9 moves us from 8 scratch registers to 4. This commit handles this change and also adds the base support for partial cache. Change-Id: Ibe050c663744285dd3e77850649236a669dadbd6 RTC: 150923 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27462 Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
* Handle 8MB reduced cache modeMarty Gloff2016-08-101-0/+1
| | | | | | | | | | | | Check scom register (0x1001181B) for reduced cache mode and expand the memory footprint appropriately, reduced 8MB or full 10MB. Change-Id: I5920572077cdcee317e7b3b9abe999e6de295459 RTC:152954 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27522 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Update purge of L3 cache during initial bootElizabeth Liner2016-06-101-3/+3
| | | | | | | | | | Change-Id: Ic6cfabbdfe8f10cf5fa1cd9a4a13093452b61978 RTC:118832 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24021 Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Doorbell Interrupt Base Support for Core/Thread WakeupBill Hoffa2016-05-061-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | This change includes: - Implementation of a generic KernelWorkItem Class - Kernel functionality for doorbell send to specific PIRs - Kernel changes to send core/thread Wakeup doorbells using doorbell_send() + placing KernelWorkItems on a cpu stack obj to be executed during doorbell wakeup - Kernel Interrupt Message handler changes to send wakeup msgs - Interrupt Resource Provider (INTRRP) Changes to handle wakeup msgs and monitor for timeouts - Changes to the IPL flow to invoke proper Core/Thread Wakeup - A basic outline (commented out) for how IPC messages can be implemented in the future Change-Id: I547fb8719bac657def561565ae11ab18cde72096 CMVC-Prereq: 992722 RTC:137564 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22815 Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Reviewed-by: Andrew J. Geissler <andrewg@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Integrate HWPs for step 15crgeddes2016-03-171-5/+17
| | | | | | | | | | | | | | | This commit includes work to create the call_HWP wrappers for istep15. RTC:133832 Change-Id: Ib0db5ac2b9b5d5f5c2967ff97794493d867fb04b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/774 Reviewed-by: A. P. Williams III <iawillia@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Richard J. Knight <rjknight@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Tested-by: Jenkins Server Tested-by: FSP CI Jenkins
* HOSTBOOT: Support fused coresBrian Stegmiller2015-12-111-1/+3
| | | | | | | | | Change-Id: I2ad133be733ee9e41590b3b8bd60bd6abe69d1a9 RTC: 126786 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22054 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* libc support for thread-local storagePatrick Williams2015-12-111-0/+4
| | | | | | | | | | RTC: 124148 Change-Id: I055885bc7d7cfc4ebd7cf1a662f677bdf4e28c62 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22313 Tested-by: Jenkins Server Reviewed-by: Richard J. Knight <rjknight@us.ibm.com> Reviewed-by: Brian Silver <bsilver@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Base kernel changes for Nimbus/CumulusCorey Swenson2015-12-111-1/+7
| | | | | | | | | Change-Id: Ic5dfde1e975453d760631335bab674919e1109e7 RTC: 126637 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/18321 Tested-by: Jenkins Server Reviewed-by: Christian Geddes <crgeddes@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Prevent out-of-order data access to FSP mailbox memory areaNick Bofferding2015-04-091-1/+16
| | | | | | | | | | | | | | | | | | - Added system call to map FSP mailbox memory with guard permission - Call new mapping in DMA area init - Propagate guard permission down to MMIO map - Apply guard permission in page fault handler - Updated debug tools to support extra bit in MMIO struct Change-Id: I8335ac7d3ef57e46d4c8b6c2b2a42b8a0bf7c4b0 Backport: release-fips830 Backport: release-fips820 CQ: SW295345 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/16307 Tested-by: Jenkins Server Reviewed-by: Brian H. Horton <brianh@linux.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* PRD: Enable support for UtilFile and prf files for HBRTSachin Gupta2015-01-161-1/+1
| | | | | | | | | | | Change-Id: I91f8157db632b6088fe64b28bf42f993d16e8b44 RTC: 119022 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/14944 Tested-by: Jenkins Server Reviewed-by: Zane Shelley <zshelle@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Christopher T. Phan <cphan@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Fix spelling mistakes using codespell.Patrick Williams2015-01-152-4/+8
| | | | | | | | | | | | - See https://github.com/lucasdemarchi/codespell Change-Id: I03e102d1ebb9473b6226fa9b6edb684fa0218a2f Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/15031 Tested-by: Jenkins Server Reviewed-by: STEPHEN M. CPREK <smcprek@us.ibm.com> Reviewed-by: Zane Shelley <zshelle@us.ibm.com> Reviewed-by: Brian Silver <bsilver@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* add IPMI Watchdog TimerAni Bagepalli2014-12-031-1/+9
| | | | | | | | | | Change-Id: I4617f5b545a3fc193e62fb7cfdf0292b394871c2 RTC: 108832 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/14232 Reviewed-by: Christopher T. Phan <cphan@us.ibm.com> Reviewed-by: Brian H. Horton <brianh@linux.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com> Tested-by: Jenkins Server
* Support for serial console.Patrick Williams2014-09-241-3/+6
| | | | | | | | | | Change-Id: Ia1b11f68cc4be175076562b7daf0291b14df498b Origin: Google Shared Technology RTC: 97495 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/13250 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Populate actual PVR value instead of architected versionDean Sanner2014-07-221-1/+9
| | | | | | | Change-Id: I5d19166fe949394fae536f5165ce6138be7f820b Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/12277 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Add Naples support to the kernelBrian Silver2014-06-231-0/+2
| | | | | | | | | Change-Id: Ie748454257938103bdb76d7ac1b5d425bc97d348 RTC: 107941 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/11298 Tested-by: Jenkins Server Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Change copyright prolog for all files to Apache.Patrick Williams2014-05-2110-117/+117
| | | | | | | Change-Id: I5664587b4f889099290ef50d50fa9ce5e580e1eb Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/11167 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Use new scratch reg for hb_done and set early in IPLAndrew Geissler2014-03-131-6/+4
| | | | | | | | | | | | | | | | | This is to support using the scratch register for the power off message. I moved to a new scratch register since we were sharing with a SBE scratch reg that was needed early in HB IPL. NOTE! This will have a co-req with an FSP track so we'll need to coordinate. CMVC-Coreq: 917527 Change-Id: I5f81f15126d6ad8d2c9459c5afe730554256c037 RTC: 95818 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/9220 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: MIKE J. JONES <mjjones@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Workaround invalid SBE use of IPI inject registerDean Sanner2014-03-041-1/+3
| | | | | | | | | Change-Id: I40600399daf2ef563b534bd91143a4f45d00ff79 CQ: SW248610 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/9273 Tested-by: Jenkins Server Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Handle pending interrupts across nodes in mpiplDoug Gilbert2014-03-021-0/+58
| | | | | | | | | RTC: 80988 Change-Id: I7ef9feaa3d163d6956576f30538e2fe001e892a1 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/8441 Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* implement start_payload for multi-drawerDoug Gilbert2014-01-101-2/+4
| | | | | | | | RTC: 71994 Change-Id: I422f349d5588731a5e7cfc504d96e497958d6b95 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/7426 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* hbirt increase number of modules allowedDoug Gilbert2013-11-131-1/+6
| | | | | | | | Change-Id: I64a05ac460d75a8328a326d808e906dc0751a8d8 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/7166 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Initial Support for Updating SBE SEEPROMMike Baiocchi2013-10-281-1/+1
| | | | | | | | | | | | | | | This initial commit will be used to create the new SBE directories and files. It also supports the usr functions to find and copy SBE PNOR images. NOTE: It will not enable Updating SBE SEEPROMs in the IPL. Change-Id: I3f545a134493c7595ce50fd885478bbe606de472 RTC: 47032 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/6311 Tested-by: Jenkins Server Reviewed-by: ADAM R. MUHLE <armuhle@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Resolve testcase race conditions with SCAN.Patrick Williams2013-09-111-2/+2
| | | | | | | | | | | | | | A number of test cases were writing to the SCAN select register and if the SCAN device driver unit tests were running at the same time they would clobber each other. Moved the other test cases to utilize a core scratch register instead. Change-Id: I243500ce40cdb75e1052541056f9460e50e0bbcd Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/5977 Tested-by: Jenkins Server Reviewed-by: MIKE J. JONES <mjjones@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Ensure task_crash not optimized outMike Jones2013-08-291-2/+2
| | | | | | | | | | | | | | User space assert() calls the task_crash() macro to crash the thread, this writes to address NULL, but the write is optimized out. Therefore an assert does not cause the task to crash as intended. If istep code asserts, the istepdispatcher does not notice and Hostboot hangs instead of TIing. This is fixed with a volatile. Change-Id: Icc27d94d76e937000189655c2f8a640620456673 RTC: 80657 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/5968 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Basic devtree supportDean Sanner2013-08-091-1/+4
| | | | | | | | | | Simple devtree support for Sapphire in SPless mode Change-Id: I4a70bfc5cd3eb3dbd1b443869c046c789f98cc95 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/3739 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Use SBE Setting of Thread Count or FailMike Baiocchi2013-07-091-23/+28
| | | | | | | | | | | | | | This commit takes out the workaround of using a default setting of a thread count if the SBE didn't set the right value in a scratch register. The current SBE code now does this, and we will now fail if for some reason the value isn't set. This commit also includes sim action file updates to model this behavior. Change-Id: I83608c402fac675c0287fa3ce38cf75237bcff26 RTC: 63991 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/5255 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Secureboot memory layout support.Patrick Williams2013-06-141-0/+1
| | | | | | | | | | | | | | | | * Start kernel in 1/4 cache mode per Secureboot. * Copy Secureboot header for base image for later use. * Blind-purge bottom half of cache. * Add bottom of cache into memory maps for 1/2 cache mode. RTC: 64762 Change-Id: I1b45f30a2d45c9709d4fd486cfe0ca2ce86b051c Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/3773 Reviewed-by: Michael Baiocchi <baiocchi@us.ibm.com> Tested-by: Jenkins Server Reviewed-by: ADAM R. MUHLE <armuhle@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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