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* Secureboot memory layout support.Patrick Williams2013-06-143-13/+26
| | | | | | | | | | | | | | | | * Start kernel in 1/4 cache mode per Secureboot. * Copy Secureboot header for base image for later use. * Blind-purge bottom half of cache. * Add bottom of cache into memory maps for 1/2 cache mode. RTC: 64762 Change-Id: I1b45f30a2d45c9709d4fd486cfe0ca2ce86b051c Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/3773 Reviewed-by: Michael Baiocchi <baiocchi@us.ibm.com> Tested-by: Jenkins Server Reviewed-by: ADAM R. MUHLE <armuhle@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Handle SLB machine check errs by resetting SLB.Patrick Williams2013-06-141-0/+7
| | | | | | | | | | Change-Id: I8a74a88e6eb812406c64976e7842903e1063021a Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/4605 Tested-by: Jenkins Server Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: ADAM R. MUHLE <armuhle@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* New mm_block_map syscall.Patrick Williams2013-06-103-34/+37
| | | | | | | | RTC: 71081 Change-Id: Ic5531fbba92cfc7aad7d303f043d6a350483d63d Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/4607 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Tolerate memory UEs during dump extraction.Patrick Williams2013-06-062-23/+67
| | | | | | | | | | Change-Id: I0dc57ec047beb47b557b816162d619a5b2a54108 RTC: 64619 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/4600 Tested-by: Jenkins Server Reviewed-by: ADAM R. MUHLE <armuhle@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Inter-processor communications for multinodeDoug Gilbert2013-05-162-1/+45
| | | | | | | | RTC: 63128 Change-Id: Ica27c7f714bc8b874c9bccb663a32d3cfba37c5a Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/4193 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Race condition in heap coalesce.Patrick Williams2013-05-151-27/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously the heap coalesce function looked at the "free" flag on the next block to determine if two blocks could be merged together. The coalesce function is ran with all cores synchronized so no one should be modifying the heap, but there is still a subtle race condition. A user task could be in the process of freeing a block, marking it "free" but not actually inserting it onto the queues yet. The coalesce will combine this block together but then when the user task resumes it continues to try to insert it onto the queue. This causes both the larger merged block and the smaller block to be on a free queue and memory corruption when both blocks are used. This is resolved by having a new flag indicating that the block is known to be part of the "coalesce" group and using this in addition to the "free" flag. Only blocks which are actually present on the free queues are considered to be part of the "coalesce" group. Change-Id: If33d15d731d32e07e01104244ebc65daf2295878 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/4520 Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Add thread-safety to kernel interrupt handler.Patrick Williams2013-04-181-5/+3
| | | | | | | | | | | | | | | | | | | | The interrupt handling was originally written with the intent that only a single thread would receive interrupts. We purposefully program the Interrupt Presenter hardware to route all interrupts to a single core. IPIs (Inter-processor Interrupts) are not routable by the ICP and end up being delivered to the targeted thread. When we trigger a winkle-wakeup of a thread, that thread gets the IPI interrupt. Since we broadcast the IPI to all threads on a core there is potential for multiple threads to be using the interrupt object at once. Hence, we added a spinlock to protect it. Change-Id: I736de774496b13cc9f344d389b9f249bbabeb036 Tested-by: Jenkins Server Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Allow winkle of all threads for multi-drawer add.Patrick Williams2013-04-082-8/+46
| | | | | | | | | | | RTC: 63124 Change-Id: I1ad1d6bdf6a2848b686b25504fabddddb701d440 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/3813 Tested-by: Jenkins Server Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Michael Baiocchi <baiocchi@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Update Core Scratch Reg 6 with L3 vs Mainstore for FSP to queryMissy Connell2013-03-262-1/+117
| | | | | | | | | RTC:64829 Change-Id: Ic8e7983f6838b79c359c4cee2647b7676493cb1e Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/3564 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Changes required for A bus and 4 dimm supportDean Sanner2013-03-261-6/+8
| | | | | | | | | Change-Id: I1670913709df9acd5cddf19feaccab6462125e5f Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/3655 Tested-by: Jenkins Server Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Support for less than 8 threads per coreDan Crowell2013-02-081-1/+2
| | | | | | | | | | | Modified anywhere that we enable non-master threads to only touch the threads that we are told to update. Change-Id: I5b764e51d85a5c663ac76164e9465831ef0c167c RTC: 48808 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/2877 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Triggering Hostboot Shutdown when PNOR is badAdam Muhle2013-02-041-1/+4
| | | | | | | | | | | | | Updating the doShutdown path to support receiving a reason code as input. Then changing PNOR RP to issue a shutdown when problems are detected with the PNOR Partition table. RTC: 44146 Change-Id: Ib4111d0a91f53d90fa100422a1463539897598e6 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/3024 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Support RPR register.Patrick Williams2013-01-141-1/+14
| | | | | | | | | | | | | | | | | | | | For P8 the priority of different threads has no effect unless the relative priority register is programmed to tell the relative scheduling weight of the different priorities. We will now be programming the RPR to give 32x performance boost to "high" priority threads relative to "low" priority. This means that when a thread is waiting on another, and thus has low priority, it will get 32x less dispatch cycles then the thread it is waiting on. Change-Id: I0d1d1052b12ab8bd5612aa4580cd85b5c238f885 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/2888 Tested-by: Jenkins Server Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: Mark W. Wenning <wenning@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Switch Interrupt Presenter to get ICPBAR value from an attributeDoug Gilbert2012-12-141-24/+26
| | | | | | | | Change-Id: I5d95f3e3e2d803f07c7d8f3bf2d8ee522e1b4519 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/2406 Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com> Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Expand memory footprint to full 8MB cache.Patrick Williams2012-11-143-27/+53
| | | | | | | | | | | | | | If fake PNOR isn't being used, we can expand our memory space to the full 8MB cache. There will be follow up work with RTC: 49137 to support 4MB degraded caches for bring-up. Change-Id: I1248efa37965f39ebab62aae556349c34aa24b66 RTC: 47356 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/2319 Tested-by: Jenkins Server Reviewed-by: Melissa J. Connell <missyc@us.ibm.com> Reviewed-by: ADAM R. MUHLE <armuhle@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Terminate Immediate on a shutdown and assertMissy Connell2012-11-095-14/+120
| | | | | | | | Change-Id: I37c8956afb11c69201f4936821cff5e153327780 RTC:43793 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/2194 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* pore_gen_cpuregMark Wenning2012-11-071-3/+5
| | | | | | | | | Change-Id: Ic5cb0817118bf0de7d706124708e5b8551ba4258 RTC: 41425 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1899 Tested-by: Jenkins Server Reviewed-by: Van H. Lee <vanlee@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Terminate Immediate Structure defintionMissy Connell2012-10-243-0/+151
| | | | | | | | | | - Add include files into the fsp.tar Change-Id: I12a50f7e09f70b1bc6acf436d896b6f3747a7507 RTC:50578 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/2115 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Memory Leak task_endBill Schwartz2012-10-122-47/+47
| | | | | | | | Change-Id: Idb7a2d8d72a55f644efd0b2548eca5df5d062e6d RTC: 47491 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/2011 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Extend VMM to 32MMissy Connell2012-10-095-82/+180
| | | | | | | | | | | | | | Add mmLinearMap to create block at a specified phys addr. Added iv_MaptoPhy in the block to indicate we are physically mapped block and to not apply the HRMOR. Change-Id: I75ddb19b82ae9a2035ff873edff8a34a33c74639 RTC:43401 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1846 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Sync timebase to slave cores.Patrick Williams2012-09-241-0/+7
| | | | | | | | | | Change-Id: I196e58be48195f653ab16a74dedafabafbd07bbc RTC: 47013 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1774 Tested-by: Jenkins Server Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Fixes for winkle state.Patrick Williams2012-09-212-23/+28
| | | | | | | | | | | | | | | | | | | The memory profiling tools sometimes encountered a condition where the kernel stack was becoming corrupted. I tracked it down to the winkle code storing the winkle-save state at the wrong end of the stack. Moving the winkle-save area to the bottom of the stack, which is where I originally intended it to go. Also noticed that the task issuing the winkle was in "running" state while waiting for the cores to come out of winkle. Ensure that the kernel updates the task state with a non-running status while we are waiting for winkle to complete. Change-Id: I07a56ea6f24cbc09362f9227d81915da5bc9f148 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1737 Tested-by: Jenkins Server Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Support for Non-zero HRMORDan Crowell2012-09-164-95/+127
| | | | | | | | | | | | | | | | | | Changes to kernel code to support detection and use of HRMOR offset in memory Changes to tooling to handle the real memory offset New interface to retrieve the physical address that corresponds to a virtual address To test, run these commands before starting up Hostboot: system_cmp0.cpu0_0_05_0.write-reg HRMOR 0x8000000 proc_venicechip_cmp0.phys_mem.del-map p8Proc0.l3_cache_ram 0 0 RTC: 46032 Change-Id: I50ab248f941218a3a14a8f0fc12a551b56dc7cf3 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1553 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Allow processors on logical nodes != 0.Patrick Williams2012-09-062-55/+81
| | | | | | | | | | | | | | | | | Created per-node arrays of CPU objects rather than a single array for the entire system. These are created dynamically as CPUs are enabled. Also disabled support for P7 due to the PIR layout being different and hence would have needed two different sets of assembly code. We have been running exclusively on the P8 Mambo model for a while. RTC: 42815 Change-Id: Ib92de8a7c07c2e700a3b7f0c03c64d484b447ca2 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1630 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Write scratch register in start_payload / shutdown.Patrick Williams2012-09-041-22/+24
| | | | | | | | | | Change-Id: I47a8ad7914c6833c476a7944be5d352f45467f3a RTC: 47725 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1646 Tested-by: Jenkins Server Reviewed-by: Mark W. Wenning <wenning@us.ibm.com> Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Support for master winkle.Patrick Williams2012-08-106-41/+316
| | | | | | | | | RTC: 44730 Change-Id: Ifaeecc659e1bfd8ded4744dc591fc993471519ba Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1471 Tested-by: Jenkins Server Reviewed-by: Mark W. Wenning <wenning@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Task structure had wrong enum size.Patrick Williams2012-08-091-1/+1
| | | | | | | | | | | | | hb-Ps debug tool gave wrong task state because the removal of compile option -fshort-enums caused the enum to grow and be in the wrong location for the debug tool to find. Change-Id: Ib0bcec1cddc648b3cee649be7e5ad258b4142bc3 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1507 Tested-by: Jenkins Server Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com> Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Execute 'doze' in idle loop.Patrick Williams2012-07-284-34/+40
| | | | | | | | | Change-Id: Ifd611129c2d7173b5e0dec36c870e06a4d851009 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1384 Tested-by: Jenkins Server Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Reduce timeslice for idle task based on wake time of sleeping tasksDoug Gilbert2012-07-281-30/+55
| | | | | | | | | RTC: 43738 Change-Id: I91c2bfe57bba04a02dd5169542de8e76e1654ae8 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1387 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* cpu_spr_value syscall for SLW image build.Patrick Williams2012-07-182-0/+17
| | | | | | | | | | | | Task 44887 Change-Id: If87b6e80b974bb4cbff13844d8a3f055a17282d2 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1378 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: Mark W. Wenning <wenning@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Support for core_activate via IPI.Patrick Williams2012-07-164-27/+49
| | | | | | | | RTC: 37009 Change-Id: I56669805c86d9659a20ad7c26e5e9860c7a248c7 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1087 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Improve user-space page allocator.Patrick Williams2012-07-161-0/+8
| | | | | | | | | | | | | | | | | * Allow page allocation system call to force coalesce if a contiguous block is unavailable. [long-term enhancement] * Workaround lack of large contiguous memory for PageTable test-cases, which require 256K, by allocating a VMM block. This should be removed when story 43401 is implemented. [short-term workaround] Change-Id: Idddb30eaa3aeac52d56b82a70355095f31d4a0cd Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1369 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Live-lock issues in memory allocator.Patrick Williams2012-07-114-59/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | * Debug tool for PageManager. * Support PageMgr allocations of non-2^k size. * Switch page-allocation to always be in kernel-mode. While investigating issue 44511, I noticed two problesm with the memory page allocator (PageManager). First, the allocator did not support allocations of pages which were not a power of 2, which would result in pages appearing to "leak". Second, in situations where a large allocation was requested and there was not a large chunk available, the allocation would enter a live-lock condition where coalescing would never occur. Switched the PageManager so that all allocations happen in kernel space. This allows us to force memory-release operations on the syscall path when we are out of memory and also put in place a task_yield call which will allow coalescing to eventually occur. Issue 44523 is suppose to fully resolve any of these live-lock paths. RTC: 44511 Change-Id: Ifefd5d0996ee6914e291c862fac0c7b76980717f Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1330 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Improve memory page manager for low memory situationsDoug Gilbert2012-07-113-68/+173
| | | | | | | | | RTC: 40831 Change-Id: I7889f91eec44a10d56ffc94e03c7557f8085100a Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1272 Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com> Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Fix FSIDD mutex issue, misc memory tweaksAdam Muhle2012-06-071-24/+25
| | | | | | | | | | | | | -Fixed Mutex issue in FSIDD -Remove FSIDD workaround for a perceived simcis bug which we now think was just the mutex issue. -Cleaned up some traces in scom.C -Temporarily disabled testCastOutPages() to avoid memory issues -Tweaked periodics in cpumgr.H Change-Id: Ic34193cc2f81a40530214cd3338dfb405d1e8198 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1171 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Pick up Simics FSI fixes for multiple chipsDan Crowell2012-05-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | Updating the Simics level to get FSI fixes to allow multiple chips to work. This also allows us to remove some previous workarounds. The new Simics build pulled in a different PNOR so needed to disable some of the tests. The new Simics build also modified some of the L3 objects so changes were required to some debug tools. Had to update the VENICE config since Ched rewired it to look like MURANO/Tuleta. Testing: Verified 2-proc, 4-centaur MURANO config Verified 2-proc, 4-centaur VENICE config Change-Id: I6aaaf8aad2f82dbfffb8ade551d545bedaa3e048 RTC: 41305 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1066 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Support for POSIX clock_gettime function.Patrick Williams2012-05-211-2/+39
| | | | | | | | | | Change-Id: I004772e9005ce08d72d666a9b4073afd7b74e582 RTC: 41635 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1053 Tested-by: Jenkins Server Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Mailbox DMA buffer capabilitiesDoug Gilbert2012-05-162-1/+6
| | | | | | | | | RTC:34032 Change-Id: Ib1e29210ffc183f9c3bd475ab8d9779b5a448909 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/932 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* INTR set IPCBAR scom reg on init and add INTR shutdown interfaceDoug Gilbert2012-05-111-0/+46
| | | | | | | | | | RTC: 39730 Change-Id: Ib548202f6f935b46cd92e0ddbf48d19b5ff6679a Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/977 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Allow kernel to shutdown-to-payload.Patrick Williams2012-04-243-0/+11
| | | | | | | | | | | | | | | This code is currently unused, due to InitService not having the payload address and the start_host_os IPL step being unimplemented. For testing purposes the 'shutdown' call in initservice.C can be changed to pass a non-zero base address (such as 256MB). RTC: 40871 Change-Id: I0f4b6bae62ede1853aabbcb28082300005e31897 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/926 Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com> Tested-by: Jenkins Server Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
* Update Periodics to avoid Out of Memory ErrorDan Crowell2012-04-231-2/+2
| | | | | | | | | | | | | I modified the settings for the periodics that run and keep free memory available. This is needed for the VENICE config to not fail with a OOM. Change-Id: I1626183acfff67c0367f4ebf3869a8c674fd1d76 RTC: 40832 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/922 Tested-by: Jenkins Server Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Optimize PageTableManager and associated VMM.Patrick Williams2012-04-188-23/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | - Changed overall page table behavior to no longer use C bits in page table entries. Instead, individual blocks mark pages as dirty based on stores during page faults. Initially all writable pages are marked read-only until the first store to it. At that time the block gets an exception and changes the permission on the page table entry to writable and marks its own SPTE to dirty. - Greatly reduced the number of tlbie's and page table accesses. Accomplished this by: * Skipping many of the page table manipulations, such as LRU updates, when the PTE is invalid. * Converting most of the previously general-case of "Modifying a PTE" to specific cases such as "Resetting the Reference Bit" and "Modifying the SW field". - Fixed the LRU-flush algorithm so that it is O(n) instead of O(n^2), where n = size of page table. Change-Id: I2520fa88970fd7f656e6348bf6b34d5db82fd3db Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/892 Tested-by: Jenkins Server Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Support P8 mambo model and Murano proc.Patrick Williams2012-03-211-2/+2
| | | | | | | | | RTC: 38206 Change-Id: Iab79041931db533ad6b6ebd057c1ef9fe4c4b8cc Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/714 Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Handle hype_fac_unavail exception.Patrick Williams2012-02-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | The P8 processor (in RFC02230 targeted for ISA 2.07) adds a new SPR register HFSCR (Hypervisor Facility Status and Control Register). This register allows the hypervisor to disable access to some resources, such as floating point and VSX, from a partition. The purpose of this is to save time in saving the partition context when switching partitions. Since we sometimes enable floating point instructions we need to also enable the HFSCR[FP]. We could do this when enabling floating point in the MSR, but the SPR does not exist in P7. Instead we'll do it as-needed on the hw-thread the first time it executes a FP instruction. The FP instruction will cause the hype_fac_unavail exception and the exception handler will set HFSCR appropriately. Change-Id: I6c1e75939bb59142cbcf692fa56deb2271d6bdc3 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/676 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* GCOV supportPatrick Williams2012-02-071-0/+1
| | | | | | | Change-Id: I73a446754cd03178055459eb75c7b2f87b51b0f3 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/635 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Conditional Variable supportDoug Gilbert2012-01-252-23/+17
| | | | | | | Change-Id: Ib715b3a4e775ef183244e8769c6560a85ac19104 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/612 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Support additional device segments and MMIO blocksPatrick Williams2012-01-183-30/+50
| | | | | | | | | Change-Id: Icd2e9ed7de2c0227b25979622d0f37a77595570a Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/609 Tested-by: Jenkins Server Reviewed-by: MATTHEW S. BARTH <msbarth@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Tool to display memory statisticsDoug Gilbert2012-01-123-3/+9
| | | | | | | Change-Id: Iaac392b9f4287ba888e454532c4061d6a14c6e5c Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/593 Tested-by: Jenkins Server Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
* Interrupt presenter implementationDoug Gilbert2012-01-051-0/+99
| | | | | | | | Change-Id: If6b499d819b71298b8a64e096e1eb83c639ad645 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/517 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
* Fix race condition between stackmanager and vmmmanager.Patrick Williams2012-01-053-0/+6
| | | | | | | | | | Change-Id: Ie3f3fb2050428af1fc398b1577dfc090cd7d26cf Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/591 Tested-by: Jenkins Server Reviewed-by: MIKE J. JONES <mjjones@us.ibm.com> Reviewed-by: Melissa J. Connell <missyc@us.ibm.com> Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: MATTHEW S. BARTH <msbarth@us.ibm.com>
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