| Commit message (Collapse) | Author | Age | Files | Lines |
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P9 moves us from 8 scratch registers to 4. This commit handles
this change and also adds the base support for partial cache.
Change-Id: Ibe050c663744285dd3e77850649236a669dadbd6
RTC: 150923
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27462
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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Check scom register (0x1001181B) for reduced cache mode and expand the
memory footprint appropriately, reduced 8MB or full 10MB.
Change-Id: I5920572077cdcee317e7b3b9abe999e6de295459
RTC:152954
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27522
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Change-Id: I5664587b4f889099290ef50d50fa9ce5e580e1eb
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/11167
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Change-Id: I74823572a4935d3c8c4d7999d8c00c0286de1523
RTC: 50233
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/5170
Tested-by: Jenkins Server
Reviewed-by: Andrew J. Geissler <andrewg@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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RTC:64829
Change-Id: Ic8e7983f6838b79c359c4cee2647b7676493cb1e
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/3564
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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