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* Force a Hostboot dump on any TI in SimicsDan Crowell2020-01-071-0/+1
* Handle processor swap between slots to 1-socket systemDan Crowell2019-08-051-0/+25
* Assembly for DARN instruction inconsistentCorey Swenson2019-06-211-5/+3
* NVDIMM encryption HW function supportCorey Swenson2019-06-031-0/+20
* Developer Improvement: Get code coverage tool working with HostbootZach Clark2019-05-131-0/+1
* General Improvement: Get HB standalone + op-build working with GCC8Luis Fernandez2019-05-021-4/+6
* Validate OMI INBAND BAR offset attributes against calculated valuesChristian Geddes2019-04-181-1/+2
* Add simics exit_cache_contained mode callMatt Derksen2019-04-081-0/+1
* Add msgsync to doorbell wakeup logic to avoid weak consistency bugDan Crowell2019-01-211-1/+15
* Elevate log levels for simics during PSU opsChristian Geddes2018-10-181-1/+37
* Support HB running in SMFDean Sanner2018-09-242-1/+10
* Base Core/Kernel Changes to Support the Axone Processor ChipBill Hoffa2018-08-201-4/+5
* Update MAGIC instruction for SimicsDan Crowell2018-06-181-2/+2
* Debug improvements for exceptions and OOM hangsDan Crowell2018-06-151-1/+2
* Add some MAGIC instructions to aid Simics optimizationDan Crowell2018-05-301-8/+25
* Force 25G Nvlink speed on P9N DD2.1Dean Sanner2018-03-081-1/+19
* Enable ATTN prior to OPAL handoffBrian Bakke2017-11-301-0/+7
* Story 180760 - Use self restore API to disable ATTN in HID ...Brian Bakke2017-11-071-0/+8
* Log traces to error logs in HBRTMatt Derksen2017-10-191-0/+10
* Setup INTP bars correctly when memory is swapped on master proccrgeddes2017-06-021-0/+5
* Map BAR attributes based on data from BootloaderDan Crowell2017-06-021-0/+61
* Cleanup for SMT4/SMT8 read fuse bits and activate threadsCorey Swenson2017-05-151-2/+0
* Fix PVR check for Nimbus DD1Dan Crowell2017-05-111-2/+10
* Handle SMT4/SMT8 fuse bitsCorey Swenson2017-04-281-0/+2
* More istep debug outputDan Crowell2017-04-171-1/+16
* Create PVR routines to handle DD2 changesDan Crowell2017-03-091-0/+135
* Multi-Proc Interrupt Support with Remote LSIsBill Hoffa2016-10-071-0/+5
* Log SBE Traces on error (simics only)Dan Crowell2016-09-281-0/+7
* Replace NAP with STOP instructionBrian Stegmiller2016-08-071-10/+1
* Add testcases for pirformat helper functionsBill Hoffa2016-05-241-7/+27
* Add simics breakpoint for exceptionsDan Crowell2016-05-241-1/+3
* Update PIR Structure to Match SpecificationBill Hoffa2016-05-171-20/+24
* Update constants and comments for P9 PIR formatDan Crowell2016-02-291-0/+167
* HOSTBOOT: Support fused coresBrian Stegmiller2015-12-111-0/+34
* P9 page table changesCorey Swenson2015-12-111-0/+15
* Base kernel changes for Nimbus/CumulusCorey Swenson2015-12-111-2/+3
* Load PAYLOAD from FFS partition.Thi Tran2014-06-301-1/+5
* Change copyright prolog for all files to Apache.Patrick Williams2014-05-211-11/+11
* Force TIs for unhandled exceptionsPatrick Williams2013-12-091-0/+17
* Fixed performance issues in SIMICS IPLStephen Cprek2013-10-311-0/+1
* Update Core Scratch Reg 6 with L3 vs Mainstore for FSP to queryMissy Connell2013-03-261-0/+13
* Load a fake payloadPatrick Williams2013-03-261-0/+1
* Support RPR register.Patrick Williams2013-01-141-1/+15
* Memory profiling tools.Patrick Williams2012-09-071-1/+2
* Set "high" thread priority as 2 rather than 3.Patrick Williams2012-09-051-24/+23
* Support for master winkle.Patrick Williams2012-08-101-2/+12
* cpu_spr_value syscall for SLW image build.Patrick Williams2012-07-181-22/+46
* Support for core_activate via IPI.Patrick Williams2012-07-161-0/+6
* Initial attention handler support.Brad Bishop2012-07-161-1/+2
* Code optimizations.Patrick Williams2012-04-161-15/+27
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