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* Shift HWP content to align with desired EKB layoutJoe McGill2016-02-193-0/+230
* Fix all incorrect copyright prologsStephen Cprek2016-02-193-3/+3
* JET: Level 1, p9_pm_pba_initBilicon Patil2016-02-193-0/+378
* New scom addresses const headers for chip 9031Ben Gass2016-02-191-117/+1
* Fix all incorrect copyright prologsStephen Cprek2016-02-192-2/+2
* Generated from n10_e9024_tp023_spider_u223_01Ben Gass2016-02-192-0/+538
* Fix all incorrect copyright prologsStephen Cprek2016-02-191-1/+1
* JET: Level 2, Make p9_pm_occ_control FAPI2.0 compilantSangeetha T S2016-02-191-4/+11
* Shift HWP content to align with desired EKB layoutJoe McGill2016-02-191-0/+62
* New scom addresses const headers for chip 9031Ben Gass2016-02-192-361/+760
* Intermediate updates for header files.Ben Gass2016-02-191-34/+1126
* Regenerated header files from e9029Ben Gass2016-02-192-1871/+3551
* Generated from n10_e9024_tp023_spider_u223_01Ben Gass2016-02-192-0/+17099
* Fix all incorrect copyright prologsStephen Cprek2016-02-192-2/+1
* p9_block_wakeup_intr Level 1Bilicon Patil2016-02-193-0/+224
* New scom addresses const headers for chip 9031Ben Gass2016-02-191-1060/+2447
* Regenerated header files from e9029Ben Gass2016-02-191-1012/+3100
* Generated from n10_e9024_tp023_spider_u223_01Ben Gass2016-02-191-0/+36512
* PM: Added make file for special wakeup HWP and fixed prolog.Prem Shanker Jha2016-02-191-0/+20
* Fix all incorrect copyright prologsStephen Cprek2016-02-194-4/+4
* Regenerated header files from e9029Ben Gass2016-02-191-0/+12
* PM: Level 1, p9_cpu_special_wakeup.Prem Shanker Jha2016-02-192-0/+131
* Shift HWP content to align with desired EKB layoutJoe McGill2016-02-191-0/+133
* Generated from n10_e9024_tp023_spider_u223_01Ben Gass2016-02-191-0/+44
* Add FAILED_TRANSLATION constant to Scom Trans codecrgeddes2016-02-192-1/+7
* Add STANDARD_MODE constant to Scom Trans Codecrgeddes2016-02-191-1/+6
* Fix all incorrect copyright prologsStephen Cprek2016-02-1919-19/+19
* HWP for p9_start_cbsAnusha Reddy Rangareddygari2016-02-191-1/+1
* p9_exit_cache_contained procedure (Level 2)Thi Tran2016-02-192-14/+33
* Updates for p9_revert_sbe_mcs_setup, p9_sbe_mcs_setup (Level 2)Joe McGill2016-02-195-58/+429
* p9_chiplet_scominit Level 1Michael Dye2016-02-193-0/+134
* p9_htm_setup procedure (Level 1)Thi Tran2016-02-196-0/+1439
* p9_setup_bars L1 deliveryJoe McGill2016-02-193-0/+162
* p9_psi_scominit procedure (Level 1)Thi Tran2016-02-193-0/+158
* p9_mss_setup_bars procedure (Level 1)Thi Tran2016-02-193-0/+334
* PCIE Level 1 proceduresJoe McGill2016-02-197-76/+162
* FBC Level 1 proceduresJoe McGill2016-02-199-0/+491
* p9_scominfo: adjust base address validity checkJoe McGill2016-02-191-5/+0
* Level 1 HWP for p9_chiplet_enable_ridiAnusha Reddy Rangareddygari2016-02-193-0/+117
* Level 1 HWP for p9_switch_cfsimAnusha Reddy Rangareddygari2016-02-193-0/+117
* Level 1 HWP p9_check_slave_sbe_seeprom_completeAnusha Reddy Rangareddygari2016-02-193-0/+120
* Level 1 HWP for p9_mem_startclocksAnusha Reddy Rangareddygari2016-02-193-0/+117
* Level 1 HWP for p9_switch_rec_attnAnusha Reddy Rangareddygari2016-02-193-0/+117
* Level 1 HWP for p9_mem_pll_setupAnusha Reddy Rangareddygari2016-02-193-0/+117
* Level 1 HWP for p9_mem_pll_initfAnusha Reddy Rangareddygari2016-02-193-0/+121
* Level 1 HWP for p9_mem_skewadjustAnusha Reddy Rangareddygari2016-02-193-0/+117
* Level 1 HWP p9_extract_sbe_rcAnusha Reddy Rangareddygari2016-02-193-0/+117
* p9_throttle_sync procedure (Level 1)Thi Tran2016-02-193-0/+193
* p9_attr_update Level 1Michael Dye2016-02-193-0/+135
* p9_mss_eff_grouping procedure (Level 1)Thi Tran2016-02-193-0/+2670
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