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path: root/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
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* Updates to permit synchronized SS PLL spreading via TODJoe McGill2018-08-201-0/+17
* apply INT ARX clock gate disable to p9n DD2.0 hardwareJoe McGill2018-08-021-1/+1
* Disable HW439321 workaround in dd1.3Adam Hale2018-08-011-0/+17
* Enable CDD1.3's 4 risklevels (step 1)Nick Klazynski2018-07-251-6/+64
* p9.pci.scan.initfile -- replace 62028 implementation with initfile entryJoe McGill2018-07-191-7/+0
* Clockgate disable workaround for HW452921Nick Klazynski2018-07-171-3/+3
* Secure memory allocation and setupJenny Huynh2018-07-131-0/+72
* set PEC disable store thread based ordering chicken switchesJoe McGill2018-07-121-0/+31
* Alink Hot Repair FixChris Steffen2018-06-291-0/+18
* Updating p9.core.scan.initfile settings for p9n 2.3Ben Gass2018-06-211-2/+16
* Add RL0/RL1 support for CDD1.2Nick Klazynski2018-06-211-8/+31
* Update p9n_23 engd with n23_e9108_3_tp105_ec408_soa_sc_u138_01 dataBen Gass2018-06-141-1/+15
* p9_sbe_scominit -- unmask TP LFIR bit 37 for CumulusJoe McGill2018-06-141-0/+17
* Adding p9c 1.3 support.Soma BhanuTej2018-05-311-1/+18
* Disable 2-for-1 on NDD2.2- and CDD1.2-Nick Klazynski2018-05-181-4/+5
* enable spreading via SS PLL for Fleetwood platformJoe McGill2018-05-181-0/+17
* Enable full ERAT for NDD2.2+ and CDD1.1+Nick Klazynski2018-05-171-0/+24
* HW447585, HW447589, HW439303, Fix CDD1.2 security settingNick Klazynski2018-05-171-1/+84
* jgr18042600 Changed rx_recal_abort_dl_mask=0 for cumulus HW446964John Rell2018-05-171-0/+24
* Savory Insomnia -- revert to ordered tlbie mode for CumulusJoe McGill2018-04-301-1/+34
* Adding p9n 2.3 support and p9n 2.3/p9c 1.2 security updateBen Gass2018-04-211-0/+41
* TM workaround for HW443982Nick Klazynski2018-04-211-4/+11
* Abist proc update for SBE changesAbhishek Agarwal2018-04-121-0/+17
* Turn off PB.IOO.LL0.CONFIG_FAST_ASYNC_CROSS for Nimbus (HW409026)Ben Gass2018-04-101-0/+18
* Do not apply HW414958 to AxoneThi Tran2018-03-261-3/+28
* HW438727 Disable clockgate to allow correct ODL error reportingJenny Huynh2018-03-231-0/+25
* Remove CDD1.1 security IMC; Apply indirect branch serialization to HV=0 onlyNick Klazynski2018-03-231-17/+0
* Disable WOF for Cumulus DD1.0Dan Crowell2018-03-131-0/+7
* Enable risklevel2, match v44 of security wikiNick Klazynski2018-03-131-3/+3
* Axone support to TP stopclocksSoma BhanuTej2018-03-131-0/+17
* Axone MC uses same pll/clock setup as in Cumulus.Ben Gass2018-03-131-1/+16
* Add support for p9c 1.2Ben Gass2018-03-131-0/+48
* Add Cumulus DD1.1 initsNick Klazynski2018-03-131-46/+291
* Protect Firmware from exposure to HW423533Lennard Streat2018-03-131-0/+18
* Add TM WAT workaround; NDD2.2 and CDD1.1 onlyNick Klazynski2018-03-131-0/+24
* Disabling WOF and VDM for Nimbus DD2.0Dan Crowell2018-03-131-2/+2
* Re-submit Axone updatesBen Gass2018-03-131-17/+234
* Enable mixed core xlate; Enable xlate protection feature; Disable LSU clockgateNick Klazynski2018-03-131-0/+72
* p9.npu.scom.initfile -- limit DCP0 credits for HW437173Joe McGill2018-03-131-0/+18
* Updating HW414700 to also apply to Cumulus DD10Jenny Huynh2018-03-131-2/+9
* Two LTPTR workarounds, remove LTPTR serialization, Fix TB IMCNick Klazynski2018-03-131-18/+32
* Remove workaround for DD1 SW reset for XIVESachin Gupta2018-03-131-18/+0
* HDCT: Remove core trace arrays, permanent P9 erratumJoachim Fenkes2018-03-131-3/+4
* Implement security IMCs, based on v29 of wikiNick Klazynski2018-03-131-6/+149
* Add new TM IMC, Add TLBIE hangbusterNick Klazynski2018-03-131-0/+24
* Fix three NDD2.1 dials and add new NDD2.2 workaroundsNick Klazynski2018-03-131-14/+189
* Zepplin:Remove dd level check for cumulus under PPB codePrasad Bg Ranganath2018-03-131-7/+0
* PM: Ignore allow_reg_wakeup in cache contained modeBrian Vanderpool2018-03-131-0/+28
* Workaround for Quaint Gate, Angry ReindeerJenny Huynh2018-03-131-4/+29
* jgr171017 Setting changes for Obus boardwire vs cableJohn Rell2018-03-131-0/+24
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