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path: root/src/import/chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C
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* Secure memory allocation and setupJenny Huynh2018-07-131-16/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | p9_mss_eff_grouping.C: - determines whether secure mem is requested, reserves smf space - always reserve smf at end of range because of end-of-range bit - set addr15 when reporting smf base address - mask off group_id(0) via chip address extension if smf is enabled - updated to set value of attr_smf_enabled - enhanced error reporting with smf config/supported values - made values reported to attr_mss_mcs_group_32 more clear p9_mss_setup_bars.C: - set MCFGPA/MCFGPMA registers with SMF data - fixed scom registers for MCFGPA/MCFGPMA hole setup - added note to leave MCFIR_invalid_smf masked for HW451708/HW451711 - added assert to check for HOLE1 and SMF enable overlaps p9_query_mssinfo.C: - updated to print out SMF reservations - print out HTM/OCC/SMF reservations regardless of mirroring enable p9_fbc_utils.C: - prevent group_id(0)=1 from affecting mappable memory ranges p9_sbe_fabricinit.C: - mask off group_id(0) via chip address extension if smf is enabled p9_setup_sbe_config.C, p9_sbe_attr_setup.C: - use scratch_reg6 bit(16) to pass smf_config value initfiles: - removed setup to use other addr bits as secure bit; core only uses addr15 - added setup for ncu addr15 value in hcode - always set addr15 config bit in bridge unit if smf is supported - set addr15 bit across all mcs if smf is enabled - added in settings to enable smf in nmmu unit - hardcode group_id(0) bit in chipext mask for bridge unit if smf is supported attributes: - ATTR_SMF_ENABLE is a system level attribute - changed SMF_ENABLE->SMF_CONFIG; smf_enabled will be (config && supported) CQ:HW451708 CQ:HW451711 Change-Id: I6cf85600354baa322e959c922f596ecc5c68a458 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57322 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Dev-Ready: Brent Wieman <bwieman@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57348 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* Temporarily moving attribute to the system targetElizabeth Liner2018-04-091-6/+6
| | | | | | | | | | | | | | | | | | | | | | There were dependency issues between the FSP and hostboot changes. This commit is temporarily moving everything to the system target, so that we can get our changes through CI. We'll go back later and fix the target to the proc Change-Id: Ic2d63d10afe50342290a814a94fd2d07d7102fdf RTC:176434 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56814 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56827 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
* Updating ATTR_PROC_CHIP_MEM_TO_USE to use all bits of group and chip IDElizabeth Liner2018-04-091-9/+11
| | | | | | | | | | | | | | | | | | | | When first created, we assumed the group ID and chip ID's were both 2 bits, but they're actually 3. This is updating the attribute. Change-Id: Iabc112f7202d410bd7bceab53c3ad79a1df17368 RTC:176434 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56039 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56112 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
* Updating HWP's to use PROC_CHIP_MEM_TO_USE attributeElizabeth Liner2018-03-161-0/+9
| | | | | | | | | | | | | | | | | | Change-Id: I649400f7675b1df10049d05336a80accd3bf63c9 RTC:176434 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54601 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Richard J. Knight <rjknight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54674 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Additional risk level support - (step 2) Updating the image w/RL2Claus Michael Olsen2018-02-221-12/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit changes the images' .rings section by adding the TOR RL2 variant slot to the runtime Quad chiplets, EQ and EC. Specifically, we have changed the definition of the ATTR_RISK_LEVEL attribute to now have three risk levels, RL0 (prev FALSE), RL1 (prev TRUE) and RL2 (new). To accomodate RL2, a new "override" txt file has been created, ./attribute_ovd/runtime_risk2.txt and changes to many other files using the ATTR_RISK_LEVEL attrib have been updated as well. Lastly, and to allow for the inclusion of RL2 rings in the HW image, the TOR_VERSION has been updated to version 6 which will allow for RL2 support in the ring ID metadata files. p9_setup_sbe_config is updated to write the RISK_LEVEL value into scratch 3 bits 28:31, and deprecate the existing mailbox. RISK_LEVEL processing has been removed from p9_sbe_attr_setup. It's only function is to seed mailboxes which are empty via the attribute state present in the SEEPROM. Since RISK_LEVEL is zero at image build time, and explicitly cleared as a result of every customization, there's logically no need to process the RISK_LEVEL here. PPE changes to accomodate the new RISK_LEVEL mailbox location need to be implemented in the PLAT code: src/hwpf/target.C Key_Cronus_Test=XIP_REGRESS HW-ImageBuild-Preqeq=52659 - 52659 must be fully merged in Cronus and HB before this commit (53292) can be merged. This is to avoid a Coreq situation. CQ: SW416424 cmvc-prereq: 1046058 cmvc-prereq: 1043606 cmvc-prereq: 1045920 Change-Id: Ia0471219916602cc0041a2c55a1070013f66a7d9 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53292 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Richard J. Knight <rjknight@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53321 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* Fix failures to boot with unsecured modeJaymes Wilks2018-01-241-1/+5
| | | | | | | | | | | | | | | | | | | | | Fixes the problem of slave SBEs causing hangs due to propagation of istep mode bit of ATTR_BOOT_FLAGS. Change-Id: I3c7ebe5626b6fbfb54e40a78c7d2ec69d2bde5df CQ:SW413592 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52267 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52409 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* p9_setup_sbe_configAnusha Reddy Rangareddygari2017-11-271-55/+222
| | | | | | | | | | | | | | | | | | | In scom mode to run on HB Change-Id: Ia0d5654133cdec247e7e16669961e69e16f11291 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49593 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49596 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* Update hardware procedure metadataAnusha Reddy Rangareddygari2017-10-051-1/+1
| | | | | | | | | | | | | | | | | | | | update the metadata to reflect that HWPs are product ready (HWP Level: 3) Change-Id: I5a7380e9f34865b3e0ef7872d6338a840b08aa4a Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46789 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46793 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* mc_pll_bucket attributeAnusha Reddy Rangareddygari2017-07-111-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | in async mode for Cumulus. Using scratch_reg_2 bits 21:23 shift p9_xip_customize changes to a separate, dependent commit to satisfy HB CI for this commit Change-Id: I44c25c5cfb437298f1102f5275a260b4c5ccf522 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42355 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42357 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* add support for OBUS PLL bucketsJoe McGill2017-06-221-3/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | p9_frequency_buckets.H p9.obus.pll.scan.initfile document and support base frequencies 1611 MHz - 25.78G, 156.25 MHz ref 1250 MHz - 25G, 156.25 MHz ref 1200 MHz - 19.2G, 133.33 MHz ref pervasive_attributes.xml define ATTR_OB[0123]_PLL_BUCKET to hold encoded ring bucket select value nest_attributes.xml define ATTR_FREQ_O_MHZ array to hold per chiplet OBUS frequency retain ATTR_FREQ_A_MHZ to serve as FBC A link frequency indicator p9_setup_sbe_config.C p9_sbe_attr_setup.C transmit bucket selection through FSP/BMC->SBE mailbox encode OBUS bucket selects in Scratch Reg2 bits 24:31 p9_sbe_chiplet_pll_initf.C p9_sbe_chiplet_pll_initf_errors.xml scan correct ring image based on bucket selector attributes p9_ringId.C p9_ringId.H p9_ring_id.h accomodate three copies of obX_pll_bndy (use ID previously reserved for obX_pll_func, which should not be necessary to scan init) scan_procedures.mk generateWrapper.pl initCompiler infrastructure changes to support build of bucket data p9.fbc.ab_hp.scom.initfile p9.fbc.ioo_tl.scom.initfile p9_tod_setup.C updates to handle A,O frequency attribute changes Change-Id: I42f9bb4037a587f7e3ec8dd9848bdb853ac3d7a0 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40159 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40165 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* support chip swap in memory map via FBC XOR mask programmingJoe McGill2017-05-221-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | p9_sbe_fabricinit.C p9.fbc.ab_hp.scom.initfile set PB_CFG_XLATE_ADDR_TO_ID based on XOR of effective & absolute FBC group/chip ID attribute values, prior to island mode FBC init cleanup register/field constant todos p9_fbc_utils.C parametrize p9_fbc_utils_get_chip_base_address to support calculation of origin address based on: - effective FBC group/chip ID attributes (EFF_FBC_GRP_CHIP_IDS) - effective FBC drawer origin -- effective FBC group ID + chip ID=0 (EFF_FBC_GRP_ID_ONLY) - absolute FBC group/chip ID attributes (ABS_FBC_GRP_CHIP_IDS) p9_sbe_mcs_setup.C (MCS BAR for HB dcbz support) set p9_fbc_utils_get_chip_base_address call to use EFF_FBC_GRP_ID_ONLY configures BAR address based on drawer base + HRMOR p9_sbe_load_bootloader.C set p9_fbc_utils_get_chip_base_address call for bootloader load to use EFF_FBC_GRP_ID_ONLY (drawer) store XSCOM/LPC BAR into bootloader config data structure in exception vector (based on chip offset) p9_mss_eff_grouping.C (MCS/HTM BARs) p9_pcie_config.C (PCIE MMIO BARs) p9_rng_init_phase2.C / p9_hcode_image_build.C (NX RNG BAR) p9_sbe_scominit.C (XSCOM/LPC BARs) p9_setup_bars.C (MCD, FSP/PSI/NPU/INT MMIO BARs) set p9_fbc_utils_get_chip_base_address call to use EFF_FBC_GRP_CHIP_IDS p9_setup_sbe_config.C p9_sbe_attr_setup.C transmit ATTR_PROC_EFF_FABRIC_[GROUP/CHIP]_ID via scratch6 mailbox p9_xip_customize.C init ATTR_PROC_EFF_FABRIC_[GROUP_CHIP]_ID to zero in image Change-Id: I3f30bc81a986872c2e7f47422b96bf7bf7c59b06 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37261 Reviewed-by: Matt K. Light <mklight@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37777 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* literal definitionsAnusha Reddy Rangareddygari2017-04-071-4/+5
| | | | | | | | | | | | | | | | | | instead of constants in the optimized procs Change-Id: I761ec79dc173465cd502844b6e2da7eff7dd800c Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37954 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38025 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* support customization of Nimbus DD1 PCI reference clock speedJoe McGill2017-03-291-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | rename existing EC feature attribute, now serves as DD1N enable qualifying application of MRW-sourced ATTR_DD1_SLOW_PCI_REF_CLOCK: 0 = NORMAL = 100 MHz 1 = SLOW = 94 MHz MRW attribute is plumbed through SBE mailbox (scratch 5 bit 5, value inverted) and added to XIP customize CMVC-Prereq:1020384 Change-Id: I376f06d0d49ab3d39c965e3131d484cbe9535566 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38129 Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38135 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Control NDL training updateAnusha Reddy Rangareddygari2017-02-071-22/+74
| | | | | | | | | | | | | | Change-Id: I13d721d7fb1d71c58314dd1e09006a7b4df0dee2 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35211 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35217 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* configure FBC pump mode in SBEJoe McGill2017-01-181-0/+17
| | | | | | | | | | | | | | | Change-Id: Ia4e69cf50548e355cfb7cbf5e67be48e61427ffa Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34318 Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34349 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
* Security control override disable support - p9_setup_sbe_configSoma BhanuTej2017-01-041-4/+4
| | | | | | | | | | | | | | Change-Id: Ia36d3ed31614976c25bef144c45396f577f037b7 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33401 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33403 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Change chip to unsecure always for DD1 chipsSoma BhanuTej2016-10-121-1/+20
| | | | | | | | | | | | | | | Change-Id: I73e2aace7ad9a56bfd528b4b2d82741148df971f RTC:158131 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30952 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30955 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Setup ATTR_OBUS_RATIO_VALUE for SBE platformThi Tran2016-09-241-10/+19
| | | | | | | | | | | | | | | | | Change-Id: Ib9db247cf20b084a0106dd7b65819060ea1fc2ca Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29568 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29579 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
* PLL configuration updates -- permit e2e bypass executionJoe McGill2016-09-041-23/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | p9_sbe_attr_setup p9_setup_sbe_config transmit PLL bypass controls through MBOX Scratch 4 bits 16:20 transmit PLL mux controls through MBOX Scratch 5 bits 12:31 p9_common_poweronoff increase polling delays to account for refclock speed p9_hcd_cache_dpll_setup permit DPLL execution in bypass, based on ATTR_DPLL_BYPASS p9_sbe_npll_setup permit NEST PLL execution in bypass, based on ATTR_NEST_MEM_X_O_PCI_BYPASS p9_mem_pll_setup permit MEM PLL execution in bypass, based on ATTR_NEST_MEM_X_O_PCI_BYPASS p9_sbe_chiplet_pll_setup permit X/O/PCI PLL execution in bypass, based on ATTR_NEST_MEM_X_O_PCI_BYPASS p9_sbe_tp_switch_gears skip adjustment of i2c bit divisor, based on ATTR_NEST_MEM_X_O_PCI_BYPASS p9_sbe_attributes.xml hb_temp_defaults.xml add defaults to enable platform CI Change-Id: Icba6aee79d90b0280ba4818afd92c344c52f52ef Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28611 Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28614 Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Update prologs of mirrored files to apache licenseStephen Cprek2016-08-051-8/+14
| | | | | | | | Change-Id: I25a782f6f8af801beb35f541f6076c482b78bf8e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27920 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Matthew A. Ploetz <maploetz@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* FAPI_INF entering and exiting message updatesAnusha Reddy Rangareddygari2016-08-041-2/+2
| | | | | | | | | | | | Change-Id: Iac3116df68febfd228e7e0dc19c30526ac932906 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27804 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27805 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* scan HWP updatesJoe McGill2016-08-041-4/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | tested via Cronus platform putring implementation p9_sbe_attr_setup p9_setup_sbe_config adjust mailbox write/read logic to properly handle cache contained mode p9_sbe_gptr_time_initf remove unused MC mc_iom[01|23]_time rings add OBUS1/2 scans add PCI pci[0|1|2]_pll_gptr rings add N2 n2_psi_gptr ring p9_sbe_repr_initf remove unused MC mc_iom[01|23]_repr rings add OBUS1/2 scans p9_sbe_nest_initf skip MC iom[01|23]_fure scans which require DETERMINISTIC_TEST_EN p9_sbe_io_initf skip PCI pci[0|1|2]_fure scans which require DETERMINISTIC_TEST_EN remove DETERMINISTIC_TEST_EN application for XB p9_hcd_cache_initf remove explicit initfile invocation/ring caching in wrapper correct putring targeting add EX ex_l2_mode ring scan p9_hcd_core_initf remove explicit initfile invocation/ring caching in wrapper add EC ec_mode ring scan add DBG/ERR trace for all putRing calls remove unused *gptr_time_repr_initf HWPs and wrappers Change-Id: If1f8e9f5b327a6ab4f9b5271c53616ad20163b93 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27400 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27402 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Level 2 HWP for p9_setup_sbe_configAnusha Reddy Rangareddygari2016-05-191-1/+8
| | | | | | | | | | | | | | Change-Id: I906fcea684ead022a71d822d90b8380a20797838 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24768 Tested-by: Jenkins Server Tested-by: Hostboot CI Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: ARAVIND T. NAIR <aravindnair@in.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24769 Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Level 2 HWP for p9_sbe_attr_setup,p9_setup_sbe_configAnusha Reddy Rangareddygari2016-05-161-130/+179
| | | | | | | | | | | | | | | Change-Id: Ib3c07a029d28c4923b2e8dee32bd8067a13d67a5 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24365 Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Sangeetha T S <sangeet2@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24506 Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Level 2 HWP p9_setup_sbe_configSunil.Kumar2016-02-251-13/+156
| | | | | | | | | | | Change-Id: Ie24a17f5a9ef3688e6bd2c8122dc42aa8422d068 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/21038 Tested-by: Jenkins Server Reviewed-by: Anusha Reddy Rangareddygari <anusrang@in.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Parvathi Rachakonda Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/24802 Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* L1 Rev istep 0.(6-8,11,13,14),1.1,2.(1-13,15,18-20,22,26,27,30,32,34) V2Abhishek Agarwal2016-02-251-0/+46
Change-Id: Ie1609875aac5177e2f39dead5d3d96f0c36a955d Original-Change-Id: I3ea0eec08ce479057277524021bfce540d7b63ca Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/17755 Reviewed-by: Brian Silver <bsilver@us.ibm.com> Tested-by: Brian Silver <bsilver@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/24799 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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