summaryrefslogtreecommitdiffstats
path: root/src/import/chips/p9/procedures/hwp/perv/p9_set_fsi_gp_shadow.H
Commit message (Collapse)AuthorAgeFilesLines
* Update hardware procedure metadataAnusha Reddy Rangareddygari2017-10-051-1/+1
| | | | | | | | | | | | | | | | | | | | update the metadata to reflect that HWPs are product ready (HWP Level: 3) Change-Id: I5a7380e9f34865b3e0ef7872d6338a840b08aa4a Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46789 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46793 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* p9_pre_poweron, p9_set_fsi_gp_shadow: Merge flush values, fix ROOT_CTRL2(5)Joachim Fenkes2017-06-131-2/+2
| | | | | | | | | | | | | | | | | | | | | Have pre_poweron use constants from p9_set_fsi_gp_shadow so we only have one additional copy of the flush values outside of the VHDL itself. Also fix ROOT_CTRL2(5) so that PIB traces actually capture request and response data after IPL. Change-Id: I01dc1132de5953c2853ff395cce0ede3aac434d7 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41579 Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41581 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Don't raise VDD2VIO fence on warm IPLJoachim Fenkes2016-10-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | The VDD2VIO fence will disable the Nest PLL, preventing the global endpoint reset from propagating. This may cause a high VCS current state to reappear, tripping the VCS voltage regulator. The fence is only required for the initial voltage ramp-up state and doesn't need to be set during warm boot. This change will cause the CBS to lower the fence on a cold boot as well, but it would have been lowered in the next CBS state anyway, so there's no harm done here. Change-Id: I3f10e74351ac925fbfb3040a08ddce3b34576efa CQ: HW390523 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31371 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31384 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Update prologs of mirrored files to apache licenseStephen Cprek2016-08-051-8/+14
| | | | | | | | Change-Id: I25a782f6f8af801beb35f541f6076c482b78bf8e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27920 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Matthew A. Ploetz <maploetz@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* VBU IPL -- update sim PLL configurationJoe McGill2016-07-201-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Adjust refclock/PLL configuration to drive all mesh clocks from PLLs non-IO/wafer configuration (nest PLL bucket #1) -- default for sc/sq/fc IO/system model configuration (nest PLL bucket #2) -- default for mc Regression framework updates Remove dependence on sim-only varosc/refclock HWPs Scan from HW image (ultimately need to move to SEEPROM) Add memory attribute HWPs missing from flow Handle real/broadside scan options HWP updates Scan PLL configuration from image Preserve clock mux attribute programming First crack at removing unneeded PLL buckets from images/TOR Add boot support for warm IPL Change-Id: Ic7f27ab3dfdf258471d91618adc8eae4cadb2e42 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26938 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26939 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Level 2 HWP for p9_set_fsi_gp_shadowAnusha Reddy Rangareddygari2016-06-101-0/+18
| | | | | | | | | | | | | | Change-Id: If08c3550b6f8b8a3efc158d1eaaa3234d22b7bb5 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25604 Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: Sunil Kumar <skumar8j@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25606 Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Level 2 HWP for p9_set_fsi_gp_shadowAnusha Reddy Rangareddygari2016-06-011-18/+0
| | | | | | | | | | | | | | Change-Id: Icb0bd70104ce8659a8e22aaca21864caf69846ff Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24796 Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: Sunil Kumar <skumar8j@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24799 Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* p9_set_fsi_gp_shadow - updates RC init valuesAnusha Reddy Rangareddygari2016-05-121-2/+2
| | | | | | | | | | | | | Change-Id: Ia93e881caf6cfc1e6316995cec629eefea9c25a6 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24240 Tested-by: Jenkins Server Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Tested-by: Hostboot CI Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24242 Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Level 2 HWP for p9_set_fsi_gp_shadowAnusha Reddy Rangareddygari2016-02-251-9/+25
| | | | | | | | | | | Change-Id: I382f9a0088fafca0c8918299960049066c2e17f4 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/23825 Tested-by: Jenkins Server Reviewed-by: Sunil Kumar <skumar8j@in.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: Parvathi Rachakonda Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/24803 Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* L1 Rev istep 0.(6-8,11,13,14),1.1,2.(1-13,15,18-20,22,26,27,30,32,34) V2Abhishek Agarwal2016-02-251-0/+55
Change-Id: Ie1609875aac5177e2f39dead5d3d96f0c36a955d Original-Change-Id: I3ea0eec08ce479057277524021bfce540d7b63ca Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/17755 Reviewed-by: Brian Silver <bsilver@us.ibm.com> Tested-by: Brian Silver <bsilver@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/24799 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
OpenPOWER on IntegriCloud