| Commit message (Collapse) | Author | Age | Files | Lines |
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Attributes:
-------------------------------------------------------------------------------
nest_attributes.xml
add ATTR_LINK_TRAIN, written by platform on X, O endpoints to specify
whether half or full link should be trained
add ATTR_PROC_FABRIC_LINK_ACTIVE, written by p9_fbc_eff_config_links
adjust enums for ATTR_PROC_FABRIC_[XA]_ATTACHED_CHIP_CNFG, written
by p9_fbc_eff_config_links
add ATTR_PROC_FABRIC_[XA]_LINKS_CNFG, written by p9_fbc_eff_config_links
pervasive_attributes.xml
create ATTR_PROC_NPU_REGION_ENABLED to encapsulate accessibility of
NPU logic domain, written by p9_chiplet_scominit
chip_ec_attributes.xml
add EC feature attribute controlling DL training workaround
Initfiles:
-------------------------------------------------------------------------------
p9.fbc.ab_hp.scom.initfile
add logic to permit reset of chg_rate master dials in second phase SMP build
adjust link enable expressions to reflect new ATTACHED_CHIP_CNFG enums
p9.fbc.cd_hp.scom.initfile
p9.fbc.no_hp.scom.initfile
consume number of configured X/A links from new attribute, simple addition
won't work any longer given new ATTACHED_CHIP_CNFG enums
p9.fbc.ioe_dl.scom.initfile
support half-link operation, based on ATTR_LINK_TRAIN on X endpoint target
p9.fbc.ioe_tl.scom.initifle
adjust link enable expressions to reflect new ATTACHED_CHIP_CNFG enums
p9.fbc.ioo_dl.scom.initfile
support half-link operation, based on ATTR_LINK_TRAIN on O endpoint target
qualify OLL enablement based on use as active fabric link
adjust PHY training parameters based on current lab learning
p9.fbc.ioo_tl.scom.initfile
adjust link enable expressions to reflect new ATTACHED_CHIP_CNFG enums
support half-link operation, based on ATTACHED_CHIP_CNFG
qualify TOD_ENABLE to apply only to O links carrying X traffic
p9.npu.scom.initfile
clear OPTICAL_IO_CONFIG when not actively using NVLINK, finer-grained
updates needed to support mix of O SMP and NVLINK usage
HWPs:
-------------------------------------------------------------------------------
p9_io_obus_dccal
execute only on links actively carrying fabric protocol
p9_io_obus_linktrain
p9_io_regs
encapsulate PHY FIFO reset sequence needed prior to FBC DL training execution
p9_chiplet_scominit
p9_npu_scominit
partial good updates for NPU region
p9_fab_iovalid
adjust iovalid manipulation/checking, as well as link delay reporting, to
support half-link configuration
p9_smp_link_layer
support half-link configuration via ATTR_PROC_FABRIC_[XA]_ATTACHED_CHIP_CNFG
implement OBUS PHY specific workarounds
p9_eff_config_links
update ATTR_PROC_FABRIC_[XA]_ATTACHED_CHIP_CNFG to support half-link
configuration
write ATTR_PROC_FABRIC_LINK_ACTIVE on X/O endpoint targets
write ATTR_PROC_FABRIC_[XA]_LINKS_CNFG to reflect total number of logically
configured links, for initfile consumption
Istep wrappers:
-------------------------------------------------------------------------------
p9_build_smp_wrap
correctly loop over all system targets for second phase SMP build
p9_sys_chiplet_scominit_wrap
initial release
Change-Id: Ic1d87df4d3ff0feca7ac2437fa61b6d2fc4a2d68
CQ: HW419022
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43905
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: DANIEL C. HOWE <dchowe@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46997
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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Change-Id: I062d8361b2ff8c5f0327963ac6c6af7340f4086d
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41033
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Benjamin Gass <bgass@us.ibm.com>
Reviewed-by: Peng Fei Gou <shgoupf@cn.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41034
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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redefine EC feature attributes, using inverse logic where required, to qualify
inits specific to P9N DD1 where possible, to eliminate need for updates for
future chips in plan
attempt to remove usage of generic P9N_DD1_SPY_NAMES and P9N_DD2_SPY_NAMES
attributes added to support initial P9NDD2 engineering data -- several spies
were not being set as a result
-----------------
initfile updates:
-----------------
p9.cme.scan.initfile
add HW391162, SCAN_SICR_TLBIE_QUIESCE feature attributes
p9.core.common.scan.initfile
remove fused core init, it was applying scan default for P9N DD1 and is
not needed for P9N DD2+ given fuse controls
p9.core.scan.initfile
add CORE_P9NDD1 to qualify P9N DD1 specific register hierarchy and
dial programming
replace usage of P9N_DD1_SPY_NAMES, P9N_DD2_SPY_NAMES using CORE_P9NDD1
and inverse, to pick up initial pass at P9C DD1 inits
p9.cxa.scom.initfile
add CXA_P9NDD1_SPY_NAMES to qualify P9N DD1 specific register hierarchy
p9.ddrphy.scom.initfile
add DDRPHY_P9NDD1_SPY_NAMES to qualify P9N DD1 specific register hierarchy
p9.dpll.scan.initfile
remove POSTDD1N_DPLL_SETTINGS feature attribute, use DD1_DPLL_SETTINGS
attribute and inverse to drive inits
p9.l2.scan.initfile
invert definition of OPTIMAL_LARX_STCX_PERF, HW409069 feature attributes
p9.l3.scan.initfile
p9.l3.scom.initifle
remove OPTIMAL_LCO_SCOM, HW396230_SCOM feature attributes
use HW386657, HW396230 attributes to drive inits
p9.mca.scom.initfile
add MCA_P9NDD1_ASYNC to differentiate asynchronous boundary crossing
programming and dial name differences between P9N DD1, P9N DD2
p9.mmu.scan.initfile
p9.mmu.scom.initfile
invert definition of NMMU_DMT_DD2, NMMU_ISS734_DD2_1 feature attributes
p9.ncu.scan.initfile
p9.ncu.scom.initifle
remove HW396230_SCOM, use HW396230 attribute to drive inits
p9.npu.scom.initfile
remove usage of P9N_DD1_SPY_NAMES, refactor CONFIG_ENABLE_PBUS specification
to work for both P9NDD1, P9NDD2 ENGD
p9.obus.scan.initfile
remove EC qualification of OBUS FIR mask for simulation
sample.ec.scan.initfile
remove testcase requiring use of P9N_DD1_SPY_NAMES, properties of
testcase are covered by other tests
-----------------
HWP updates:
-----------------
p9_xip_customize
add customization of epsilon attributes for NMMU application
p9_chiplet_scominit
invert definition of P9_NDL_IOVALID feature attribute
remove usage of P9N_DD1_SPY_NAMES
p9_npu_scominit
replace usage of P9N_DD1_SPY_NAMES with SETUP_BARS_NPU_DD1_ADDR
p9_sbe_tracearray
invert definition of CORE_TRACE_SCOMABLE feature attribute
p9_sim_get_nia
remove usage of P9N_DD1_SPY_NAMES, directly process CT/EC attributes
(ok as this HWP is used for VBU sim only and not consumed by FW)
Change-Id: I63bfe8a4bfb8824b94e35a3688a6c69eecc1cf01
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40911
Reviewed-by: SHELTON LEUNG <sleung@us.ibm.com>
Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40916
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Change-Id: I2915e0b76c16f1c789700c0ca300e601fd0c4cdd
RTC:171599
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39676
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39689
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
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Enabling 20 caused generated initfile procedures to
change.
Chip target needed to be added to p9.fbc.ioo_dl.scom.initfile
Change-Id: Id24aa67f8d2c3f07ef85ed3bf8a555c85b4a0d72
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38324
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: CHRISTINA L. GRAVES <clgraves@us.ibm.com>
Reviewed-by: Richard J. Knight <rjknight@us.ibm.com>
Reviewed-by: Benjamin Gass <bgass@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38327
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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p9.npu.scan.initfile
initial release, mask updates for HW403585
p9_npu_scominit
configure XTS ATRMISS register
Change-Id: Id77aad7833a7fe0c3ab2cf0710a63b215a966a80
CQ: HW403585
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36393
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Reviewed-by: RYAN BLACK <rblack@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36721
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Change-Id: I4e86a8c484fa260692a78d5ff20687a8b11af826
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31693
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Dev-Ready: Brent Wieman <bwieman@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Kevin F. Reick <reick@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31745
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
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Change-Id: I25a782f6f8af801beb35f541f6076c482b78bf8e
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27920
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matthew A. Ploetz <maploetz@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Change-Id: Ib946b39da91de1ada676571ba98050045718258c
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26339
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: CHRISTINA L. GRAVES <clgraves@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26343
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Change-Id: Ie50db6d3ac63d54ade37cf69bbd009838d3b0611
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/21421
Tested-by: Jenkins Server
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/23152
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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