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path: root/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C
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* Add exp_scrubAlvin Wang2019-05-071-1/+2
* Revert "Adds exp_draminit_mc"Jennifer A. Stofer2019-02-051-1/+1
* Adds exp_draminit_mcAlvin Wang2019-02-051-2/+2
* Moves fir reg to generic folderAlvin Wang2018-12-171-1/+1
* Updates training steps factory to be LRDIMM capableStephen Glancy2018-10-151-1/+6
* Moves count_dimm to be in the memory generic folderStephen Glancy2018-04-051-1/+1
* Updates training advanced and adds custom WR CTRStephen Glancy2018-01-131-2/+2
* Worksaround AWAN simulation failureStephen Glancy2017-11-271-1/+3
* Updates dramint training structureStephen Glancy2017-11-101-1/+7
* Move around recording bad bits to prevent reconfigJacob Harvey2017-10-111-1/+6
* Updates error paths for PRD FIR checkingStephen Glancy2017-10-021-1/+1
* Implementing draminit_training_advJacob Harvey2017-08-291-1/+5
* Fix draminit_training error logging and unit testJacob Harvey2017-08-191-74/+18
* L3 draminit and mss_libJacob Harvey2017-07-261-13/+15
* Set HB to ignore draminit_training failsJacob Harvey2017-06-301-21/+59
* Added register reset functionality for DD2Stephen Glancy2017-06-071-2/+7
* Turn off PHY refresh for RD_CNTR - RD_VREFJacob Harvey2017-06-071-0/+4
* Remove ZQCAL redundant CCS inst, move to draminit_trainingAndre Marin2017-05-251-21/+24
* L3 procedure work for p9_mss_draminit_trainingJacob Harvey2017-04-071-2/+2
* Disable RTT_WR during WR_LEVEL cal step, and set equivalent terminationsLouis Stermole2017-03-151-34/+2
* Updates to run HW VREF cal by defaultStephen Glancy2017-03-011-6/+2
* Set MSS blue waterfall workaround to only run after coarse rd/wr cal stepLouis Stermole2017-02-101-2/+7
* Add DP16 API and unit testing needed to set PBA mode for LRDIMMsAndre Marin2017-02-071-2/+1
* Added periodic cal fix - fixes bad delaysStephen Glancy2017-01-301-0/+4
* Move SEQ ODT Write Configuration from draminit_training to scominitAndre Marin2017-01-161-7/+5
* Fixed WR VREF settings bugStephen Glancy2017-01-041-0/+1
* Add Memory Subsystem FIR supportBrian Silver2016-12-081-1/+6
* Added WR VREF latch commandStephen Glancy2016-11-041-1/+1
* Change bad bit processing to process bad bit attributesBrian Silver2016-10-311-0/+21
* Add disabled bit processing for DDR PHY initial calibrationBrian Silver2016-10-191-2/+21
* Changes to limit DLL cal on spare DP8, stop CSS before startingBrian Silver2016-10-161-9/+6
* Add register API for PHY Rank Pair registersLouis Stermole2016-09-201-1/+1
* Change SEQ timings, SEQ ODT, WC config and DQS polarityBrian Silver2016-09-121-5/+0
* Add implementation of ATTR_MSS_MRW_PERIODIC_MEMCAL_MODE_OPTIONSBrian Silver2016-08-171-2/+3
* Update prologs of mirrored files to apache licenseStephen Cprek2016-08-051-8/+14
* Change procedures to support unpopulated MCBrian Silver2016-07-131-0/+9
* Update error handling for IPL proceduresBrian Silver2016-06-101-35/+1
* Add eff_config functionality needed for RIT, fix cas_latency bug & attr filesAndre Marin2016-05-191-2/+2
* Change PHY PC, RC and DP16 register blocks to functional APIBrian Silver2016-05-041-1/+1
* Change draminit_mc mcbist subtest to perform compares rather than ECCBrian Silver2016-04-211-1/+4
* Add phy control error checking, clean up dp16, apbBrian Silver2016-03-221-1/+1
* Change procedure include pathsBrian Silver2016-03-181-1/+1
* Add ability to disable port fails for trainingBrian Silver2016-03-181-0/+4
* Add p9_mss_dump_regs wrapper, remove from proceduresBrian Silver2016-03-141-2/+0
* Change WC to follow the new register block patternBrian Silver2016-03-021-7/+0
* Add dump_regs for PHY registersBrian Silver2016-02-221-2/+2
* Change polling to include probes, add granular training controlsBrian Silver2016-02-221-10/+49
* Add PHY RC class, update setup cal for 2D wc/rcBrian Silver2016-02-221-1/+0
* Changes related to model 31, attr changes for sim latenciesBrian Silver2016-02-221-1/+3
* Added mss::get/putScomBrian Silver2016-02-221-3/+3
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