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path: root/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.C
Commit message (Expand)AuthorAgeFilesLines
* Moves count_dimm to be in the memory generic folderStephen Glancy2018-04-051-2/+2
* Fix order of sequence for register control words, and CKE levelsAndre Marin2017-09-051-5/+6
* L3 draminit and mss_libJacob Harvey2017-07-261-13/+34
* Turn off PHY refresh for RD_CNTR - RD_VREFJacob Harvey2017-06-071-6/+0
* Add PHY sequencer refresh settings after draminitAndre Marin2017-05-121-0/+7
* Add 500us delay after RESET_n & turn on clks before RESET_n to meet JEDEC specAndre Marin2017-03-131-8/+14
* Add Memory Subsystem FIR supportBrian Silver2016-12-081-8/+3
* Add DDR4 data buffer control words (BCWs) infrastructure & UT's.Andre Marin2016-12-061-3/+20
* Change parity error FIR clear from after MRS to beforeBrian Silver2016-10-301-3/+4
* Add RCD parity, clear parity FIR before trainingBrian Silver2016-10-171-7/+7
* Changes to limit DLL cal on spare DP8, stop CSS before startingBrian Silver2016-10-161-3/+10
* Changes for PHY zctl, bb lock, force_mclk_lowBrian Silver2016-10-121-5/+2
* Update prologs of mirrored files to apache licenseStephen Cprek2016-08-051-8/+14
* Update error handling for IPL proceduresBrian Silver2016-06-101-2/+2
* Add count_dimmBrian Silver2016-04-211-1/+10
* Change procedure include pathsBrian Silver2016-03-181-2/+2
* Initial commit of memory subsystemBrian Silver2016-02-221-6/+95
* Include .H files in their respective C files to avoid compilation errorPrachi Gupta2016-02-191-0/+1
* Change Memory L1 proceduresBrian Silver2016-02-191-0/+48
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