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talos-hostboot
04-15-2018
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p9
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phy
Commit message (
Expand
)
Author
Age
Files
Lines
...
*
Turn off PHY refresh for RD_CNTR - RD_VREF
Jacob Harvey
2017-06-07
1
-10
/
+19
*
Adds DCD empty files for DD2 code
Stephen Glancy
2017-05-31
2
-0
/
+48
*
Updated RD_VREF for DD2
Stephen Glancy
2017-05-25
2
-17
/
+77
*
Remove ZQCAL redundant CCS inst, move to draminit_training
Andre Marin
2017-05-25
4
-68
/
+66
*
Removes traits to mirror DD2 hardware
Stephen Glancy
2017-05-22
3
-11
/
+0
*
Adds DCD calibration control attributes
Stephen Glancy
2017-05-22
1
-0
/
+7
*
Add DLL workaround and unit tests
Andre Marin
2017-05-12
3
-26
/
+112
*
Added DQS alignment workaround
Stephen Glancy
2017-05-12
2
-13
/
+32
*
Move index API to generic/memory folder
Andre Marin
2017-05-12
3
-2
/
+3
*
Add PHY sequencer refresh settings after draminit
Andre Marin
2017-05-12
2
-0
/
+139
*
Fixes RD VREF runtime calculation
Stephen Glancy
2017-05-07
3
-4
/
+8
*
Added read ctr bad delay workaround
Stephen Glancy
2017-04-27
1
-5
/
+35
*
Increasing CCS polling limit for HB timeout
Jacob Harvey
2017-04-27
1
-3
/
+3
*
Change accesses to IS_SIM to use mss accessor
Jacob Harvey
2017-04-20
1
-4
/
+4
*
Fix up setup_cal and vref attrs
Jacob Harvey
2017-04-17
4
-27
/
+27
*
L3 procedure work for p9_mss_draminit_training
Jacob Harvey
2017-04-07
1
-19
/
+29
*
Change accesses to IS_SIM to use mss accessor
Jacob Harvey
2017-04-07
1
-1
/
+1
*
Move find API to share among memory controllers
Andre Marin
2017-03-22
4
-4
/
+4
*
Move scom API to share among controllers
Andre Marin
2017-03-18
12
-14
/
+14
*
Updates code to run PHY DCD calibration
Stephen Glancy
2017-03-16
2
-170
/
+5
*
Change accesses to IS_SIM to use mss accessor
Jacob Harvey
2017-03-16
1
-8
/
+8
*
Disable RTT_WR during WR_LEVEL cal step, and set equivalent terminations
Louis Stermole
2017-03-15
3
-31
/
+499
*
Add pos API to be shared among controllers, move generic files to utils
Andre Marin
2017-03-15
4
-5
/
+5
*
Change accesses to IS_SIM to use mss accessor
Jacob Harvey
2017-03-10
3
-28
/
+28
*
Add DQS mux map for X8 DRAMs
Andre Marin
2017-03-02
1
-24
/
+271
*
Minor change to fix compile errors from cal_timers.H on the FSP
Aravind T Nair
2017-03-01
1
-2
/
+3
*
Updates to run HW VREF cal by default
Stephen Glancy
2017-03-01
1
-0
/
+3
*
Add workaround for DDRPHY ODT config register erratum (ODT2, ODT3 bits swapped)
Louis Stermole
2017-02-21
1
-0
/
+2
*
Fixed MPR pattern bit-ordering bug
Stephen Glancy
2017-02-13
1
-4
/
+5
*
Fixed register values for RD VREF
Stephen Glancy
2017-02-11
3
-13
/
+24
*
Fix 1R dual-drop bugs
Louis Stermole
2017-02-10
1
-42
/
+12
*
Add c_str generic API and update makefiles
Andre Marin
2017-02-10
4
-7
/
+8
*
Map from Centaur canonical rank numbering to Nimbus
Brian Silver
2017-02-07
2
-77
/
+140
*
Add DP16 API and unit testing needed to set PBA mode for LRDIMMs
Andre Marin
2017-02-07
3
-23
/
+122
*
Added periodic cal fix - fixes bad delays
Stephen Glancy
2017-01-30
2
-1
/
+96
*
Add FORCE_FIFO_CAPTURE API and UTs. scominit cleanup.
Andre Marin
2017-01-30
2
-2
/
+51
*
Move SEQ ODT Write Configuration from draminit_training to scominit
Andre Marin
2017-01-16
1
-2
/
+2
*
Change adr.H to include FET slice constants from new engd
Brian Silver
2017-01-13
1
-14
/
+8
*
Fixed WR VREF settings bug
Stephen Glancy
2017-01-04
1
-41
/
+34
*
Add settings for DDR 2N mode
Brian Silver
2016-12-14
2
-3
/
+8
*
Add EC workaround for PHY training bad bit processing
Brian Silver
2016-12-07
1
-1
/
+6
*
Adds WR VREF error logging
Stephen Glancy
2016-12-07
3
-24
/
+120
*
Add EC feature levels to MSS workarounds
Brian Silver
2016-11-11
1
-4
/
+4
*
Enable read VREF calibration
Brian Silver
2016-11-09
5
-52
/
+168
*
Add DP16 workarounds for Nimbus DD1.0
Brian Silver
2016-11-08
1
-1
/
+8
*
Change dll cal poll; look for invalid rather than success
Brian Silver
2016-11-07
1
-2
/
+2
*
Update mss_decode_shadow_regs to use library MRS decoders
Louis Stermole
2016-11-04
2
-0
/
+45
*
Change mss training to fail on any disabled bits
Brian Silver
2016-11-04
1
-4
/
+2
*
Added WR VREF latch command
Stephen Glancy
2016-11-04
2
-11
/
+30
*
Change bad bit processing to process bad bit attributes
Brian Silver
2016-10-31
3
-99
/
+329
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