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path: root/src/import/chips/p9/procedures/hwp/memory/lib/phy
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* Turn off PHY refresh for RD_CNTR - RD_VREFJacob Harvey2017-06-071-10/+19
* Adds DCD empty files for DD2 codeStephen Glancy2017-05-312-0/+48
* Updated RD_VREF for DD2Stephen Glancy2017-05-252-17/+77
* Remove ZQCAL redundant CCS inst, move to draminit_trainingAndre Marin2017-05-254-68/+66
* Removes traits to mirror DD2 hardwareStephen Glancy2017-05-223-11/+0
* Adds DCD calibration control attributesStephen Glancy2017-05-221-0/+7
* Add DLL workaround and unit testsAndre Marin2017-05-123-26/+112
* Added DQS alignment workaroundStephen Glancy2017-05-122-13/+32
* Move index API to generic/memory folderAndre Marin2017-05-123-2/+3
* Add PHY sequencer refresh settings after draminitAndre Marin2017-05-122-0/+139
* Fixes RD VREF runtime calculationStephen Glancy2017-05-073-4/+8
* Added read ctr bad delay workaroundStephen Glancy2017-04-271-5/+35
* Increasing CCS polling limit for HB timeoutJacob Harvey2017-04-271-3/+3
* Change accesses to IS_SIM to use mss accessorJacob Harvey2017-04-201-4/+4
* Fix up setup_cal and vref attrsJacob Harvey2017-04-174-27/+27
* L3 procedure work for p9_mss_draminit_trainingJacob Harvey2017-04-071-19/+29
* Change accesses to IS_SIM to use mss accessorJacob Harvey2017-04-071-1/+1
* Move find API to share among memory controllersAndre Marin2017-03-224-4/+4
* Move scom API to share among controllersAndre Marin2017-03-1812-14/+14
* Updates code to run PHY DCD calibrationStephen Glancy2017-03-162-170/+5
* Change accesses to IS_SIM to use mss accessorJacob Harvey2017-03-161-8/+8
* Disable RTT_WR during WR_LEVEL cal step, and set equivalent terminationsLouis Stermole2017-03-153-31/+499
* Add pos API to be shared among controllers, move generic files to utilsAndre Marin2017-03-154-5/+5
* Change accesses to IS_SIM to use mss accessorJacob Harvey2017-03-103-28/+28
* Add DQS mux map for X8 DRAMsAndre Marin2017-03-021-24/+271
* Minor change to fix compile errors from cal_timers.H on the FSPAravind T Nair2017-03-011-2/+3
* Updates to run HW VREF cal by defaultStephen Glancy2017-03-011-0/+3
* Add workaround for DDRPHY ODT config register erratum (ODT2, ODT3 bits swapped)Louis Stermole2017-02-211-0/+2
* Fixed MPR pattern bit-ordering bugStephen Glancy2017-02-131-4/+5
* Fixed register values for RD VREFStephen Glancy2017-02-113-13/+24
* Fix 1R dual-drop bugsLouis Stermole2017-02-101-42/+12
* Add c_str generic API and update makefilesAndre Marin2017-02-104-7/+8
* Map from Centaur canonical rank numbering to NimbusBrian Silver2017-02-072-77/+140
* Add DP16 API and unit testing needed to set PBA mode for LRDIMMsAndre Marin2017-02-073-23/+122
* Added periodic cal fix - fixes bad delaysStephen Glancy2017-01-302-1/+96
* Add FORCE_FIFO_CAPTURE API and UTs. scominit cleanup.Andre Marin2017-01-302-2/+51
* Move SEQ ODT Write Configuration from draminit_training to scominitAndre Marin2017-01-161-2/+2
* Change adr.H to include FET slice constants from new engdBrian Silver2017-01-131-14/+8
* Fixed WR VREF settings bugStephen Glancy2017-01-041-41/+34
* Add settings for DDR 2N modeBrian Silver2016-12-142-3/+8
* Add EC workaround for PHY training bad bit processingBrian Silver2016-12-071-1/+6
* Adds WR VREF error loggingStephen Glancy2016-12-073-24/+120
* Add EC feature levels to MSS workaroundsBrian Silver2016-11-111-4/+4
* Enable read VREF calibrationBrian Silver2016-11-095-52/+168
* Add DP16 workarounds for Nimbus DD1.0Brian Silver2016-11-081-1/+8
* Change dll cal poll; look for invalid rather than successBrian Silver2016-11-071-2/+2
* Update mss_decode_shadow_regs to use library MRS decodersLouis Stermole2016-11-042-0/+45
* Change mss training to fail on any disabled bitsBrian Silver2016-11-041-4/+2
* Added WR VREF latch commandStephen Glancy2016-11-042-11/+30
* Change bad bit processing to process bad bit attributesBrian Silver2016-10-313-99/+329
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