summaryrefslogtreecommitdiffstats
path: root/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors_manual.H
Commit message (Expand)AuthorAgeFilesLines
* Split nimbus and cumulus find API away from genericAndre Marin2019-08-151-2/+2
* Move MSS volt attr setters to generic folderLouis Stermole2018-12-041-0/+41
* Adds plug rule for NVDIMM in specific DIMM slotsStephen Glancy2018-02-061-1/+2
* Update HPW Level for MSS API libraryAndre Marin2017-11-011-1/+1
* Increment red_waterfall for low vdn fixJacob Harvey2017-09-261-0/+23
* Remove logic to disable memory clocks in STR if in PD_AND_STR_CLK_STOP modeAndre Marin2017-09-071-23/+0
* Fixed DLL workarounds to always runStephen Glancy2017-06-201-22/+0
* Disable mem clk stop when in STR for DD2.* onlyAndre Marin2017-06-141-0/+23
* Updated memory DD1 vs DD2 attributeStephen Glancy2017-05-241-3/+3
* Adds DCD calibration control attributesStephen Glancy2017-05-221-0/+46
* Add DLL workaround and unit testsAndre Marin2017-05-121-0/+22
* Added DQS alignment workaroundStephen Glancy2017-05-121-0/+23
* Change RD_CTR workaround val and update attr nameJacob Harvey2017-05-031-3/+3
* Added read ctr bad delay workaroundStephen Glancy2017-04-271-0/+23
* Fixed blue waterfall's error messageStephen Glancy2017-04-021-1/+1
* Fixed blue waterfall workaround bugsStephen Glancy2017-04-021-3/+1
* Move find API to share among memory controllersAndre Marin2017-03-221-1/+1
* Change accesses to IS_SIM to use mss accessorJacob Harvey2017-03-141-6/+6
* Updates to run HW VREF cal by defaultStephen Glancy2017-03-011-0/+62
* Add workaround for DDRPHY ODT config register erratum (ODT2, ODT3 bits swapped)Louis Stermole2017-02-211-1/+24
* Enable bad training bits workaround, alwaysAndre Marin2017-02-111-1/+7
* Added periodic cal fix - fixes bad delaysStephen Glancy2017-01-301-1/+26
* Disable DQS polarity workaround.Andre Marin2017-01-301-0/+5
* Add MSS customization support from CRP0 Lx MVPDJoe McGill2017-01-041-51/+1
* Add minor minor version feature support to getecidBrian Silver2016-12-191-10/+21
* Add settings for DDR 2N modeBrian Silver2016-12-141-10/+35
* Add Memory Subsystem FIR supportBrian Silver2016-12-081-1/+24
* Add EC workaround for PHY training bad bit processingBrian Silver2016-12-071-0/+25
* Add EC feature levels to MSS workaroundsBrian Silver2016-11-111-0/+219
OpenPOWER on IntegriCloud