| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Fix tWLDQSEN and IPW_WR_WR timing parameters for MSS training | Louis Stermole | 2017-11-21 | 1 | -11/+42 |
| * | Update HPW Level for MSS API library | Andre Marin | 2017-11-01 | 4 | -4/+4 |
| * | Updates memory plug rules | Stephen Glancy | 2017-11-01 | 2 | -2/+214 |
| * | Add 16Gb trfc_dlr missing timing values | Andre Marin | 2017-10-17 | 1 | -5/+5 |
| * | Fix order of sequence for register control words, and CKE levels | Andre Marin | 2017-09-05 | 1 | -0/+10 |
| * | L3 work for mss xmls | Jacob Harvey | 2017-08-18 | 1 | -1/+0 |
| * | Remove logErrors in plug_rules | Jacob Harvey | 2017-06-20 | 1 | -46/+16 |
| * | Fixes RCW timing in draminit | Stephen Glancy | 2017-06-20 | 1 | -1/+22 |
| * | Fix memory plug rules and error handling | Jacob Harvey | 2017-06-19 | 2 | -106/+201 |
| * | Fix tREFI calculation to use MRW REFRESH REQUEST RATE as opposed to TEMP RANGE | Andre Marin | 2017-06-14 | 2 | -30/+37 |
| * | L3 RAS for draminit_training, eff_config, lib | Jacob Harvey | 2017-06-11 | 2 | -11/+11 |
| * | Move memory_size API to generic folder to share among controllers | Andre Marin | 2017-04-23 | 2 | -62/+4 |
| * | Fixing tfaw and trrd calculations | Jacob Harvey | 2017-03-23 | 1 | -297/+4 |
| * | Move find API to share among memory controllers | Andre Marin | 2017-03-22 | 4 | -4/+4 |
| * | Update mss_eff_config to L3 | Jacob Harvey | 2017-03-16 | 8 | -66/+222 |
| * | Implement BC attributes and make eff_dimm class | Jacob Harvey | 2017-01-25 | 4 | -4930/+20 |
| * | Move MRS attributes to eff_config to calc LRDIMMs | Jacob Harvey | 2017-01-03 | 2 | -49/+357 |
| * | Add read cmd, precharge all cmd, and read cmd CCS instruction and unit tests | Andre Marin | 2017-01-03 | 1 | -0/+10 |
| * | Add settings for DDR 2N mode | Brian Silver | 2016-12-14 | 1 | -8/+1 |
| * | Add rank config MRW override to plug rules | Brian Silver | 2016-12-08 | 2 | -27/+129 |
| * | Add DDR4 data buffer control words (BCWs) infrastructure & UT's. | Andre Marin | 2016-12-06 | 1 | -0/+10 |
| * | Add to the scom blastah unit tests | Brian Silver | 2016-12-05 | 1 | -0/+3 |
| * | Fix RCW infrastructure for LRDIMM and RDIMMs | Andre Marin | 2016-11-10 | 1 | -1/+1 |
| * | Added WR VREF latch command | Stephen Glancy | 2016-11-04 | 1 | -0/+28 |
| * | Implement L2 eff_config_thermal, bulk_pwr_throttle | Jacob Harvey | 2016-11-01 | 2 | -2/+2 |
| * | Fixed CL and timing bugs, unit test augmentations | Stephen Glancy | 2016-10-31 | 4 | -320/+1355 |
| * | Add RCD parity, clear parity FIR before training | Brian Silver | 2016-10-17 | 1 | -8/+1 |
| * | Changes to limit DLL cal on spare DP8, stop CSS before starting | Brian Silver | 2016-10-16 | 1 | -4/+11 |
| * | Add FW/Cronus VPD integration | Andre Marin | 2016-10-13 | 1 | -85/+96 |
| * | Modify raw_card infras. to take in general raw card revs | Andre Marin | 2016-10-02 | 1 | -1/+1 |
| * | Change p9_mss_freq_system to write attributes, errors for Cronus | Brian Silver | 2016-09-30 | 1 | -39/+0 |
| * | Add an attribute to avoid the plug rules in partial good scenarios | Brian Silver | 2016-09-29 | 1 | -0/+36 |
| * | Cleaned spd xml and Added module manufacturer info | Jacob Harvey | 2016-09-29 | 2 | -0/+33 |
| * | Change WR_CNTR_FW values | Brian Silver | 2016-09-25 | 1 | -0/+40 |
| * | Add enforcement of DDR4 DRAM on Nimbus via plug rules | Brian Silver | 2016-09-21 | 1 | -2/+17 |
| * | Change VPD to better account for deconfigured chiplets | Brian Silver | 2016-09-20 | 1 | -9/+12 |
| * | Add register API for PHY Rank Pair registers | Louis Stermole | 2016-09-20 | 1 | -3/+3 |
| * | Add bit field of master ranks attribute for PRD | Brian Silver | 2016-09-15 | 1 | -1/+16 |
| * | Add SEQ timing parameters, DP16 RD Diag config 5 inits | Brian Silver | 2016-09-14 | 1 | -0/+36 |
| * | Change SEQ timings, SEQ ODT, WC config and DQS polarity | Brian Silver | 2016-09-12 | 1 | -1/+2 |
| * | Add VPD decode and attributes for DQ and CKE maps | Brian Silver | 2016-09-12 | 1 | -1/+35 |
| * | Change PHY to use GPO, RLO, WLO from VPD | Brian Silver | 2016-09-08 | 1 | -11/+33 |
| * | Changes related to PHY register review | Brian Silver | 2016-09-03 | 1 | -0/+201 |
| * | Change VPD for power on and VBU | Grover Monster | 2016-09-02 | 1 | -9/+4 |
| * | Add RCD infrastructure, remove RCD hardcodes from eff_config | Andre Marin | 2016-09-01 | 1 | -119/+381 |
| * | Avoid nullptr in vpd decode for ports with no DIMM | Brian Silver | 2016-08-31 | 1 | -9/+3 |
| * | Implement MRW attributes; dram_clks, db_util, 2n_mode | Brian Silver | 2016-08-30 | 1 | -2/+11 |
| * | Fix eff_config, remove custom_dimm | Jacob Harvey | 2016-08-30 | 4 | -329/+378 |
| * | Add rudimentary memory plug rules | Brian Silver | 2016-08-26 | 4 | -13/+407 |
| * | Change DRAM output impedance value to be from MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS | Louis Stermole | 2016-08-25 | 2 | -37/+2 |
