| Commit message (Collapse) | Author | Age | Files | Lines |
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This commit sets up the FBC trace arrays to stop on a combined response
address error, for MPIPL FFDC collection.
It also adjusts the FIR configuration for several units, to trigger
a system checkstop (based on their own LFIR) if they master a command
which recieves a combined response address error cresp, and we do
not support MPIPL from that condition. Unlike in past projects, the
FBC level cresp address error FIR bit cannot be set to checkstop (in order
to support MPIPL scenarios where the unacknowledged access eminates from
the core)
FIR action bits modified:
PSIHB bits 15:20
PBA bit 1
Change-Id: Ie569600c2c937644740636e8a33097f7979d8d6f
CQ: SW411054
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52604
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52635
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
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Change-Id: I791dd6bf2d9f458c6ba47e094e45fe63f80cef14
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34536
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Kevin F. Reick <reick@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34538
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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Change-Id: Ib2e652ad78971ac12084ce1053101c081c34b590
RTC:165584
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33566
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33569
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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-Update code generation to wrap getScom/putScom getSpy/putSpy
calls in FAPI_TRY macro to save space and be consistient with
the existing hwp procedure style.
Change-Id: I37975ec424b2b369cec200ddef8a05e650954c38
RTC:165557
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33557
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Claus M. Olsen <cmolsen@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33562
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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-When refactoring the code to support iterating over EC levels
the optimization implemented to consolidate writes to the same
scom address was inadvertently removed, this commit restores
that optimization.
Change-Id: I43109b6c1e7ed2d4ed2f84f429f86cbe50553f88
RTC:164881
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33379
Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Claus M. Olsen <cmolsen@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33381
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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-Add support for looping over various EC levels for
SCOM and Scan init files
Change-Id: I7463b71698856922829cddc0e4d8d179803a1db8
RTC:159043
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31688
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Benjamin Gass <bgass@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31858
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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p9.cme.scan.initfile
add CME LFIR settings
add EQ pervasive LFIR/XFIR settings
p9.npu.scom.initfile
update NPU_0/NPU_1 LFIR settings
p9.psi.scom.initfile
add PSI LFIR settings
p9_sbe_scominit
add LPC LFIR settings
update placeholder for pervasive LFIR/XFIR settings
(for Nest/XBUS/MC/OBUS/PCIE)
p9_sbe_tp_chiplet_init3
update TP pervasive LFIR settings
p9_pcie_config
fix bug affecting PHBBAR programming (causing invalid BAR matches)
p9_pcie_scominit
update PEC LFIR settings
p9_setup_bars_defs
update MCD LFIR settings
Change-Id: I8aaf7f40e96cde2fbd6e44fd0451e0add6584b77
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29197
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29232
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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In spy to scom translation, we didn't incorporate the bits specified
by the user in initfiles.
Change-Id: I32c9aa7f81b2d96fabc95290d35da0fdf7a54ff1
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28085
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28087
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Stephen M. Cprek <smcprek@us.ibm.com>
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Change-Id: I25a782f6f8af801beb35f541f6076c482b78bf8e
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27920
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matthew A. Ploetz <maploetz@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Change-Id: Ic5bcb120b3bafbd5d8dffbc5550812e12e5472c6
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23644
Tested-by: Jenkins Server
Tested-by: Hostboot CI
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: SHELTON LEUNG <sleung@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23645
Tested-by: FSP CI Jenkins
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Change-Id: Ic5980d684b354a4e4f205b5cb6d0d08dc01ed3ea
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22569
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Jenkins Server
Tested-by: Hostboot CI
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22678
Tested-by: FSP CI Jenkins
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Add DDR PHY initfile from John Bialas
Port system pervasive dials into MCA initfile
Patch initCompiler to support above
Pull in e9035 based engineering data
Update sim only eCMD memory procedures
DIMM behavioral inits via dials
Set DDR PHY mesa mode inits via FAC
Update selected memory HWP wrappers to default to all targets
Add DIMM definitions to sc/mc Cronus config files
Update sc/mc base attribute files to match memory config
Link all steps into Cronusflex based run_ipl
Change-Id: I6040863e2718817e467540fe23c72a5192fa8480
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22924
Tested-by: Jenkins Server
Tested-by: Hostboot CI
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22926
Tested-by: FSP CI Jenkins
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Change-Id: Ia99bb03c465c3acd6ef4937936ceb0c15d1cbfbe
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/21596
Tested-by: Jenkins Server
Tested-by: Auto Mirror
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/21772
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Change-Id: Ib53568344a88bc58049f2d0a04a8d9ed6500b531
Original-Change-Id: I8839a4c6e4d53c3394af1a5f926221dec6e48153
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/24236
Tested-by: Jenkins Server
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/21676
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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