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path: root/src/import/chips/p9/procedures/hwp/cache
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* HWP:Cache stop clocks complete fixPrasad Bg Ranganath2019-02-271-0/+9
* PM HWP: Fix bug in stop clock procedure that effects mpiplPrasad Bg Ranganath2019-02-272-23/+33
* PM:Some more cleanups in update_ec_eq procedure for core unit xstop casePrasad Bg Ranganath2018-09-041-0/+9
* PM: Increase PB Purge time for MPIPL to accommodate FleetwoodGreg Still2018-06-261-2/+2
* Reset L3 error status register for next CE/UE captureJenny Huynh2018-03-071-1/+8
* Cache/Core stop clocks: add shut down of Power Management to remove contentionsAmit Tendolkar2017-12-123-18/+55
* Share common code between p9_l2_flush and p9_l2err_linedeleteThi Tran2017-10-113-106/+19
* L3 Update - p9_hcd_cache_stopclocks HWPThi Tran2017-09-254-38/+46
* StopClocks: Fence Refresh region if L3 region clock is stoppedYue Du2017-09-141-1/+17
* PM: Remove VDM check from p9_hcd_cache_stopclocksGreg Still2017-09-071-13/+13
* Synchronous stopclk procedure for QuadSoma BhanuTej2017-08-182-14/+43
* L3 Update - p9_l3err_extract/linedelete HWPsThi Tran2017-08-074-456/+473
* L3 Update - p9_l2err_extract/linedelete HWPsThi Tran2017-08-075-684/+691
* PM: Delete deprecated attributesGreg Still2017-07-141-4/+4
* P9_l3err_extract HWP -fix bugsChen Qian2017-05-245-15/+403
* P9 L2err line delete HWPChen Qian2017-05-243-12/+118
* p9_l2err_extract -- Fix bugs and tight up output formatsPeng Fei GOU2017-05-242-14/+18
* L1 - trace array on SBEShakeeb2017-05-241-7/+6
* P9 L2/L3 cache error extractionChen Qian2017-05-249-0/+1289
* Pstate: Remove legacy VDM codeChristopher M. Riedl2017-05-121-1/+5
* HW405243/IPL: Assert/drop pcb_mux_disable around quad power offYue Du2017-04-021-5/+23
* PB Purge Scoms if PBIEQ clock domain is being stoppedRaja Das2017-02-101-2/+53
* Istep4: clean up istep4 todo items and mark them with RTCYue Du2017-02-101-1/+1
* cache/core/l2_stopclocks updatesYue Du2017-02-101-22/+52
* Fix for the EKB build failure caused by hcd constantSangeetha T S2017-02-101-1/+2
* CORE/CACHE: core/cache/l2_stopclocks Level 2Yue Du2017-02-102-10/+132
* CORE/CACHE: add Level1 cache/l2/core stopclocks proceduresYue Du2017-02-103-0/+151
* Istep4: clean up istep4 todo items and mark them with RTCYue Du2017-02-071-2/+2
* cache/core/l2_stopclocks updatesYue Du2016-10-301-21/+51
* Update prologs of mirrored files to apache licenseStephen Cprek2016-08-053-24/+42
* Fix for the EKB build failure caused by hcd constantSangeetha T S2016-08-011-1/+2
* CORE/CACHE: core/cache/l2_stopclocks Level 2Yue Du2016-08-013-7/+159
* Level 1 HWP for p9_stopclocksSoma BhanuTej2016-08-012-7/+3
* CORE/CACHE: add Level1 cache/l2/core stopclocks proceduresYue Du2016-08-013-0/+142
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