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* Automatically set VPD cache flags based on EEPROM cache settingDan Crowell2019-10-171-26/+4
| | | | | | | | | | | | | | | | Added more logic to the vpd/HBconfig file to force the correct (use hardware) values for the VPD code if the EECACHE flag (SUPPORT_EEPROM_CACHING) is set. This allows the system config files to not include the unused VPD flags anymore. Change-Id: I87f7c5f3e51e3121c081b3007164dbf21cbafba8 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/84757 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R Geddes <crgeddes@us.ibm.com> Reviewed-by: Corey V Swenson <cswenson@us.ibm.com> Reviewed-by: William G Hoffa <wghoffa@us.ibm.com>
* Force sbe update loop if a change in OMI freq is detectedChristian Geddes2019-07-171-0/+3
| | | | | | | | | | | | | | After we parse the SPD to determine correct frequency settings we need to check if the optimal settings found differ from the original settings we booted with. This commit adds a check for OMI frequency changes in addition to the existing nest frequency and mc sync mode checks. Change-Id: Icaf64eda225df3aab82a033866663e3103cef55f RTC: 207596 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78739 Reviewed-by: Daniel M Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M Crowell <dcrowell@us.ibm.com>
* Add planar vpd support to Axone simicsMatt Derksen2019-06-241-1/+10
| | | | | | | | | | | | | | | | Simics support was added so now we can read directly from hardware. Change-Id: I161a847377c7271d14bf94b2e1fa7c3c63c2530c RTC:209309 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78305 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Roland Veloz <rveloz@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Unset CONSOLE_OUTPUT_ERRORDISPLAY in axone configChristian Geddes2019-06-121-0/+1
| | | | | | | | | | | | | | | We recently enabled the CONSOLE config flap to test the lpc console in simics. This caused a lot of slowdown during the test cases when we force a bunch of errors. This commit disables diplaying errors to the console in axone simics. Change-Id: I80f7868d80e4186d8034a0326d09a290d599ed07 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78777 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* Enable the UART console in Axone Simics configDan Crowell2019-06-031-0/+3
| | | | | | | | | | | | | | | Enable the code to support the console output and force Simics to display it. Change-Id: Ie7aaad150ce9191cf53387af8d147f293d98126a Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78196 Reviewed-by: Ilya Smirnov <ismirno@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Force Axone simics to read all VPD from HW with config flagsChristian Geddes2019-05-141-15/+13
| | | | | | | | | | | | | | | | | | This commit will set the config flags to always read from HW rather than the old VPD cache in PNOR. Until this point in Axone we were still using an old copy of MVPD that we write into PNOR during the startup simics scripts. From this commit onward we will use the actual VPD simics provides. To handle this, some updates we needed to the PG rules for Axone. Change-Id: Ie06cefe1aec37edfc4c379ee1173bc51fc6bbe1f Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76519 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Matt Derksen <mderkse1@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Enable IPLTIME_CHECKSTOP_ANALYSIS in axoneMatt Derksen2019-04-251-4/+4
| | | | | | | | | | Simics now supports the enablement so we now pass istep 6.11 (host_start_occ_xstop_handler) Change-Id: Ibc57795d645e98d7585eb45a122e3d127f16bbf1 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75563 Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Run Axone simics all the way to completion by defaultChristian Geddes2019-04-191-3/+2
| | | | | | | | | | | | | | | | Prior to this commit we ended the IPL at istep 14.7 and ran the CXX test suite before shutting down. This commit will allow us to run through istep 21 like a standard IPL. Change-Id: Ifb567dc30e7ecbb31ed59889ff900411633844bf Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76098 Reviewed-by: Matthew Raybuck <matthew.raybuck@ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Matt Derksen <mderkse1@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Compile Explorer MSS libs in our istepsmss libChristian Geddes2019-04-031-0/+3
| | | | | | | | | | | | | | | | We added P9A awhile back but forgot to add in the explorer libs. Some of the MSS hwps are requiring these so we need to add them. When we pulled this in it caused the HBI image for the Nimbus and Cumulus standalone layouts to be too large. To get around this we will not compile any Axone/Explorer HWP code in non-axone system configurations. Change-Id: I041f5f160a6e530995bbb1b350a1b2362704fbc8 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75224 Reviewed-by: Matt Derksen <mderkse1@us.ibm.com> Reviewed-by: Corey V. Swenson <cswenson@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Tested-by: Christian R. Geddes <crgeddes@us.ibm.com>
* Force VPD IO through HW (Axone) ,add plat function to get OCMB VPDRoland Veloz2019-03-071-2/+16
| | | | | | | | | | | | | | | | | This commit follows up on previous work that pulled in the code that can find the correct EFD given a SPD blob of data which has the DDR SPD and the EFD for the DDIMM. This commit adds ocmb_spd.C which provides a DeviceFW::SPD read interface for OCBM targets, and hooks is up to the platform implementation of the FAPI interface platGetVPD for OCMB target. Also this commit forces all VPD IO in Axone to go through HW, which will actually read from the new EEPROM cache in pnor. RTC: 203718 Change-Id: I270500898c422d4c78daa3b917b1b2e5b049e856 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72165 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Method to execute testcases early in the bootDan Crowell2019-02-281-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | A new CONFIG variable has been created that will trigger the istep dispatcher to start the CXX unit test execution at some point during the boot rather than waiting until the end. This is useful for quick targeted testing and also for early bringup of new platforms. CONFIG_EARLY_TESTCASES is the new flag, and it uses ATTR_EARLY_TESTCASES_ISTEP to determine where in the boot to stop. Changes were required in several testcases to either skip the test completely (typically due to not having enough memory) or to add additional logic to load new support libraries on demand. The Axone platform has this flag enabled by default to execute testcases at the end of istep 6.9 (host_gard). Change-Id: I1da9479e2147d68102f44d60e064c3b79cc41bb6 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71693 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Roland Veloz <rveloz@us.ibm.com> Reviewed-by: Matt Derksen <mderkse1@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
* Support reading UCD flash update LIDsNick Bofferding2019-02-181-0/+1
| | | | | | | | | | | | | | | | | | | - Added support to read a single LID container and securely verify it - Added new compile flag CONFIG_UCD_FLASH_UPDATES to enable/disable future TI UCD9090/UCD90120A flash updates - Created shell function to hold the UCD flash update logic Change-Id: I94f3e43558af5d7951febdf6ff0685c120d2db0e RTC: 201992 CMVC-Prereq: 1076388 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71945 Reviewed-by: Marshall J. Wilks <mjwilks@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Ilya Smirnov <ismirno@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Add new path in EEPROM device op to allow reading from new EECACHEChristian Geddes2019-02-161-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | Recently a new EECACHE section was introduced to Hostboot. This section gets populated with a copy of every PRIMARY_VPD eeprom (someday could contain other eeprom roles also) during host_discover_targets. This commit add support to allow users to select where they want to perform their EEPROM device operation. If they pass CACHE to the deviceOp macro then a read will come from the pnor cache, writes will write to pnor cache and then also write to the eeprom HW. If HARDWARE is passed in then reads and writes will be directly done on the eeprom hardware. If AUTOSELECT is passed the code will check our cache to see if we have a copy of the eeprom in question, if we have a copy we will go the CACHE path, if no copy exists we will go the HARDWARE path. Along with this change some reorganization was done w/ the eeprom related files. RTC: 196805 Change-Id: If2c4e5d3e338a1a10780740c1a019eb4af003b73 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70822 Reviewed-by: Matt Derksen <mderkse1@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Roland Veloz <rveloz@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Add EEPROM caching device opChristian Geddes2019-02-131-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | This commit introduces a new EEPROM_CACHE deviceOp and registers the OCMB_CHIP, PROC, and DIMM targets to it. This is part of the larger effort to transition for a "VPD" cache to an "EEPROM" cache in pnor. The deviceOp is currently called in hwasPlat's platPresenceDetect if the target in question has a ATTR_EEPROM_VPD_PRIMARY_INFO associated with it. The layout for the new EECACHE section in pnor is defined in eepromCache_const.H. Essentially it is a header that contains an array of record headers that tell where in the EECACHE pnor section a given cached EEPROM can be found. All EEPROM targets will be allocated space in the EECACHE section but only present targets will have their cache filled in. RTC: 196805 Change-Id: I49c341c9784be04ddf0259bd444f06c9baf8c6f1 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70520 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Matt Derksen <mderkse1@us.ibm.com> Reviewed-by: Roland Veloz <rveloz@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Disable NVDIMM Trigger Before Draminit and Deassert DDR_RESETn During MPIPLTsung Yeung2019-02-121-0/+1
| | | | | | | | | | | | | | | | | | | | - Per the JEDEC spec, DDR_RESETn is masked from the DRAM when the NVDIMM is armed. This could cause the training to fail if the trigger is not disabled before training. Two scenarios where this can happen are warm reboot and cold boot before the backup power module can deplete the charge - Deassert DDR_RESETn in MPIPL before triggering the restore. - Fix the config flag to enable NVDIMM code Change-Id: I9d25c2f653fc54d379f0dbab49218f5b59a407a0 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70035 Reviewed-by: Matt Derksen <mderkse1@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Add temporary Axone simics workarounds to progress IPLChristian Geddes2019-02-051-0/+8
| | | | | | | | | | | | | | | | | | | | Currently there is no VRM hooked up to the other side of the AVSbus in simics. The simics team is working on this but for now we need to skip the istep that calls setup evid to set voltages. This can be removed when Simics gets this working. Also for now we are will skip starting checkstop handling early on in the IPL because the OCC model is not finished. This also can be changed when the model starts working. Change-Id: Ia0df49fedae97acceefe07e3f3c903bbe6aac83d Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71097 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Matt Derksen <mderkse1@us.ibm.com> Reviewed-by: Corey V. Swenson <cswenson@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Enable NVDIMM code on FSP-based systemsMatt Derksen2019-01-241-0/+2
| | | | | | | | | | | | | | | | CONFIG_NVDIMM needs to be set to enable NVDIMM functionality. Change-Id: Ia1c14ea293d301ee638713fa2413a614019f8a3d Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70604 Reviewed-by: TSUNG K. YEUNG <tyeung@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Roland Veloz <rveloz@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Add new pnorLayoutAxone.xml w/ new EECACHE sectionChristian Geddes2019-01-141-0/+0
| | | | | | | | | | | | | | | | | | | | This commit introduces a new pnor layout which will be used when the simics_axone.config file is used. (Note: axone.config was renamed to simics_axone.config). This new layout introduces the EECACHE section which will be used to store copies of the various EEPROMS in the system. The eventual goal is to be able to remove the MVPD/DJVPD sections in PNOR and only use this EECACHE section Change-Id: Ifae610c4dd7f3aa9c87a5ca911cc4faa1ba2a98a Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70172 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Matt Derksen <mderkse1@us.ibm.com> Reviewed-by: Roland Veloz <rveloz@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Driver changes to support i2c muxRoland Veloz2018-12-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | - Updated data structures gpioAddr_t, eeprom_addr_t, misc_args_t, nvdimm_addr_t and tpm_info_t with I2C MUX data members. Also added constructors to these structures to default there data members with the correct default info. - Updated macros DEVICE_I2C_PARMS, DEVICE_I2C_ADDRESS and DEVICE_I2C_ADDRESS_OFFSET to take the I2C MUX bus selector parameter and the I2C MUX entity path. - Added method i2cAccessMux to file i2c.H/.C that will setup the call for the I2C MUX. Method i2cCommonOP calls i2cAccessMux which then calls i2cCommonOp with appropriate parameters for the I2C MUX: i2cCommonOP -> i2cAccessMux -> i2cCommonOP. - Updated i2ctest.H with new I2C MUX params to get it to pass. RTC:191352 Change-Id: I6a70860eb2286bbd23d6157d72351b8adfa21aac Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66651 Reviewed-by: Ilya Smirnov <ismirno@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Secure Boot: Enabled final Secure Boot settings for ZeppelinNick Bofferding2018-06-041-1/+0
| | | | | | | | | | | | | | | | - Force TPM_REQUIRED to 1 in various XML models (by not overriding default) - Remove old reference to SECUREBOOT_BEST_EFFORT policy in HBConfig - Double initial TPM log size Change-Id: Ibc9a2075ec5e490a876415d5743da40984f172f7 RTC: 187292 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59776 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com> Reviewed-by: ILYA SMIRNOV <ismirno@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Refactor SecureBoot Workarounds to better control leniencyStephen Cprek2017-08-251-0/+2
| | | | | | | | | | | | | | | | | | At this time we are trying to secure OpenPOWER in secure mode, but allow best effort policies in other scenarios Change-Id: I9ec2b5be49dbfcff678c4d30bb85f8762e448cb6 RTC: 170136 RTC: 155374 RTC: 168021 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43640 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com> Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Add new config used specifically for exporting attributes for MRWcrgeddes2017-08-251-0/+2
| | | | | | | | | | | | Change-Id: I50c26590d4f630872bace56ae999619de9fea3b6 RTC: 178497 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45144 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Elizabeth K. Liner <eliner@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Resolve istep mode issue with istep 18 on FSP systemsJaymes Wilks2017-08-031-1/+1
| | | | | | | | | | | | | | | | | Resolves the situation on FSP in istep mode where the high watermark is unable to advance beyond step 18 due to an empty non-null entry the steps array. Change-Id: If1a20aac114625c4b166b92594ad4dd83af82e02 CQ:SW397912 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44163 Reviewed-by: Stephen M. Cprek <smcprek@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
* fixed compilation errors when IPLTIME_CHECKSTOP_ANALYSIS is enabledZane Shelley2017-06-091-0/+1
| | | | | | | | | | | | | | | | Not all compile errors have been resolved because occCheckstop.C is not getting built at this time. This config will not be enabled as default until after the IPL support is complete. Change-Id: I9b2892c9bcae1929de2c871a71174a2f27d88d76 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41181 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Caleb N. Palmer <cnpalmer@us.ibm.com> Reviewed-by: Benjamin J. Weisenbeck <bweisenb@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* fixed compilation errors when ENABLE_CHECKSTOP_ANALYSIS is enabledZane Shelley2017-06-081-0/+4
| | | | | | | | | | | | Change-Id: Ic77f03ca0b4c221eef37581e6791ab8b4398af74 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41180 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Reviewed-by: Caleb N. Palmer <cnpalmer@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Enable PM during IPL on OPAL with FSPCorey Swenson2017-05-231-1/+1
| | | | | | | | | | | | Change-Id: Ie77e49aed0603f39109ddf8da2e23e3e0bcac959 CQ:SW388147 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40280 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Reviewed-by: Stephen M. Cprek <smcprek@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* move all non-volatile/openpower attributes from _hb to _openpower filesPrachi Gupta2017-05-011-0/+2
| | | | | | | | | | | | | | | | | | | When pushing hb's attr/target type files to common-mrw-xml repo, we add tags to represent which attributes are for openpower (bmc based system) and which are for fsp based systems. All attributes in _hb files are considered common for both platforms and do not have any tag. All attributes in _openpower will get openpower tag and be only shown to a system engineer if they are building a bmc based system. Therefore, the source of the attribute file is important from now on. Change-Id: I213348f4c4f372b0610b07ad3453f08f75d02224 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38161 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Matthew A. Ploetz <maploetz@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Change disable of SBE UpdatesMarty Gloff2017-03-071-1/+1
| | | | | | | | | | | | | | unset NO_SBE_UPDATES in fsprelease.config set SBE_UPDATE_DISABLE to 1 in genHwsvMrwXml.pl Change-Id: Ic0bde9a4ff573eb7e7eba180ded7324677457c90 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36696 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Elizabeth K. Liner <eliner@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Disable SBE updates on FSP based systemsDean Sanner2017-02-081-1/+1
| | | | | | | | | Change-Id: Iad4a918c37ccbcbb525937dd55ca24b39daa468e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36133 Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Enable updates of SBE SEEPROMsMarty Gloff2017-01-301-1/+1
| | | | | | | | | | | | | Unset NO_SBE_UPDATES in fsprelease.config. Create ATTR_SBE_UPDATE_DISABLE to allow disabling updates. Change-Id: Ic57d4e7a28d3778f6959d7665052ac7e9c9f73c7 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35288 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Corey V. Swenson <cswenson@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Fix the FSP config fileCorey Swenson2017-01-161-26/+4
| | | | | | | | | | | Change-Id: Idb49b6af2ebe5eacf86ed938ef0403fc3cc75e48 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34862 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Start PM Complex during IPL for OPALCorey Swenson2017-01-041-0/+4
| | | | | | | | | | | | | | | | | | | - load/start PM complex in istep21 - make some rt_pm functions common - load/start PM by default in HB standalone - load OCC image into PNOR - fix bug in UtilLidMgr - add patch for p9n.act bug Change-Id: I6c41934cf1614018da7dcad67573c3edc2d081b6 RTC:159931 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32918 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* SBE Update fixes and patches for Bring-upMarty Gloff2016-12-021-0/+1
| | | | | | | | | | | | | | | | | Set NO_SBE_UPDATE in fsprelease.config. Patch eepromdd.C to make write cycle time a minimum of 10 msec. Find .hbbl section before attempting to append new HBBL to SBE image and delete it if it already exists. Use malloc rather than stack space for ring section buffer. Fix i_maxImgSize value passed to procCustomizeSbeImg. Fix SBE_ECC_IMG_MAX_SIZE calculation to include pad bytes. Change-Id: I632e17851830acb1b365abc92438b0356232487c Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32487 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Matt Derksen <v2cibmd@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Tested-by: William G. Hoffa <wghoffa@us.ibm.com>
* HDAT changes for Witherspoonnagurram-in2016-11-141-0/+22
| | | | | | | | Change-Id: I942362604938fe4f7511e21da9246236a939c176 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30905 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Update VPO config to 2.4 Ghz nest to for sync modeDean Sanner2016-10-041-0/+2
| | | | | | | | | | | | | - Update SPD for VPO settings - Update IS_SIMULATION ATTR for VPO Change-Id: I6d92fd91f783569719efb48f3685c3a733c23fe1 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29784 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Remove core reduction based on PR fieldDan Crowell2016-09-261-1/+0
| | | | | | | | | | | | | The PR field that specifies the number of cores to enable in a given FRU has been removed for P9. Instead, the PG keyword in the module vpd will be the only indicator of the good cores. Change-Id: Ib22a5779b6beba7a4da19659f7c003a8fffb0855 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29339 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Updates to compile for P9 BMC_AST2400 istep controlDean Sanner2016-09-201-0/+2
| | | | | | | | | | Change-Id: I260b0c00053733043718f606037f60a836ef621f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25796 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-by: Matthew A. Ploetz <maploetz@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Add P9 vpo build config, config compile and extra traces for debugPrachi Gupta2016-06-061-0/+5
| | | | | | | | | | | Change-Id: Id377c921327940cc7b720e601dada4af2068d94e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22177 Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
* Adding support for FSP-specific Configuration in P9Elizabeth Liner2015-12-111-0/+6
Change-Id: I61e700eb38e0d844301d10a0a2cfabf49719606a RTC:141340 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/21973 Tested-by: Jenkins Server Reviewed-by: PRACHI GUPTA <pragupta@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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