diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/include/usr/hwpf/istepreasoncodes.H | 1 | ||||
| -rw-r--r-- | src/makefile | 2 | ||||
| -rw-r--r-- | src/usr/hwpf/hwp/dram_initialization/dram_initialization.C | 86 | ||||
| -rw-r--r-- | src/usr/hwpf/hwp/dram_initialization/makefile | 5 | ||||
| -rw-r--r-- | src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.C | 197 | ||||
| -rw-r--r-- | src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.H | 121 | ||||
| -rw-r--r-- | src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config_errors.xml | 30 | ||||
| -rw-r--r-- | src/usr/hwpf/hwp/initfiles/p8.pe.phase2.scom.initfile | 65 | ||||
| -rw-r--r-- | src/usr/hwpf/makefile | 4 |
9 files changed, 478 insertions, 33 deletions
diff --git a/src/include/usr/hwpf/istepreasoncodes.H b/src/include/usr/hwpf/istepreasoncodes.H index cf4f8a4d5..85785bb0c 100644 --- a/src/include/usr/hwpf/istepreasoncodes.H +++ b/src/include/usr/hwpf/istepreasoncodes.H @@ -100,6 +100,7 @@ enum istepModuleId ISTEP_HOST_START_PAYLOAD = 0x33, ISTEP_PROC_CHECK_SLAVE_SBE_SEEPROM_COMPLETE = 0x34, ISTEP_PROC_PCIE_SCOMINIT = 0x35, + ISTEP_PROC_PCIE_CONFIG = 0x36, }; /** diff --git a/src/makefile b/src/makefile index 2d8b48e81..9c967bd35 100644 --- a/src/makefile +++ b/src/makefile @@ -83,7 +83,7 @@ include ${ROOTPATH}/src/usr/diag/prdf/common/prd_ruletable.mk # image later. hbicore_DATA_MODULES = sample.if p8.dmi.scom.if cen.dmi.scom.if \ p8.fbc.scom.if mbs_def.if mba_def.if cen_ddrphy.if \ - p8.pe.phase1.scom.if \ + p8.pe.phase1.scom.if p8.pe.phase2.scom.if \ dimmspd.dat centaur.sbe_pnor.bin procmvpd.dat \ procpore.dat ${PRDR_RULE_TABLE_TARGETS} diff --git a/src/usr/hwpf/hwp/dram_initialization/dram_initialization.C b/src/usr/hwpf/hwp/dram_initialization/dram_initialization.C index edffb9420..8e8579829 100644 --- a/src/usr/hwpf/hwp/dram_initialization/dram_initialization.C +++ b/src/usr/hwpf/hwp/dram_initialization/dram_initialization.C @@ -43,6 +43,7 @@ #include <trace/interface.H> #include <initservice/taskargs.H> #include <errl/errlentry.H> +#include <errl/errludtarget.H> #include <diag/mdia/mdia.H> #include <diag/attn/attn.H> #include <initservice/isteps_trace.H> @@ -68,7 +69,7 @@ // #include "mss_thermal_init/mss_thermal_init.H" #include "proc_setup_bars/mss_setup_bars.H" #include "proc_setup_bars/proc_setup_bars.H" -// #include "proc_pcie_config/proc_pcie_config.H" +#include "proc_pcie_config/proc_pcie_config.H" #include "proc_exit_cache_contained/proc_exit_cache_contained.H" #include <hwpf/plat/fapiPlatReasonCodes.H> //remove these once memory setup workaround is removed @@ -86,6 +87,7 @@ using namespace ISTEP_ERROR; using namespace TARGETING; using namespace EDI_EI_INITIALIZATION; using namespace fapi; +using namespace ERRORLOG; // // Wrapper function to call 14.1 : @@ -605,47 +607,71 @@ void* call_proc_pcie_config( void *io_pArgs ) { errlHndl_t l_errl = NULL; + IStepError l_stepError; + TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_proc_pcie_config entry" ); -#if 0 - // @@@@@ CUSTOM BLOCK: @@@@@ - // figure out what targets we need - // customize any other inputs - // set up loops to go through all targets (if parallel, spin off a task) + TARGETING::TargetHandleList l_procTargetList; + getAllChips(l_procTargetList, TYPE_PROC ); - // dump physical path to targets - EntityPath l_path; - l_path = l_@targetN_target->getAttr<ATTR_PHYS_PATH>(); - l_path.dump(); + for ( TargetHandleList::iterator l_iter = l_procTargetList.begin(); + l_iter != l_procTargetList.end(); ++l_iter ) + { + const TARGETING::Target* l_pTarget = *l_iter; - // cast OUR type of target to a FAPI type of target. - const fapi::Target l_fapi_@targetN_target( - TARGET_TYPE_MEMBUF_CHIP, - reinterpret_cast<void *> - (const_cast<TARGETING::Target*>(l_@targetN_target)) ); + // dump physical path to targets + EntityPath l_path; + l_path = l_pTarget->getAttr<ATTR_PHYS_PATH>(); + l_path.dump(); - // call the HWP with each fapi::Target - FAPI_INVOKE_HWP( l_errl, proc_pcie_config, _args_...); - if ( l_errl ) - { - TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR : .........." ); - errlCommit( l_errl, HWPF_COMP_ID ); - } - else - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS : .........." ); + // build a FAPI type of target. + const fapi::Target l_fapi_pTarget( TARGET_TYPE_PROC_CHIP, + reinterpret_cast<void*>(const_cast<TARGETING::Target*>(l_pTarget)) ); + + // call the HWP with each fapi::Target + FAPI_INVOKE_HWP( l_errl, proc_pcie_config, l_fapi_pTarget ); + + if ( l_errl ) + { + /*@ + * @errortype + * @reasoncode ISTEP_DRAM_INITIALIZATION_FAILED + * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE + * @moduleid ISTEP_PROC_PCIE_CONFIG + * @userdata1 bytes 0-1: plid identifying first error + * bytes 2-3: reason code of first error + * @userdata2 bytes 0-1: total number of elogs included + * bytes 2-3: N/A + * @devdesc call to proc_pcie_config failed, see error log + * identified by the plid in user data 1. + */ + l_stepError.addErrorDetails(ISTEP_DRAM_INITIALIZATION_FAILED, + ISTEP_PROC_PCIE_CONFIG, + l_errl ); + + // capture the target data in the elog + ErrlUserDetailsTarget(l_pTarget).addToLog( l_errl ); + + errlCommit( l_errl, HWPF_COMP_ID ); + + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR : proc_pcie_config" ); + + break; + } + else + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS : proc_pcie_config" ); + } } - // @@@@@ END CUSTOM BLOCK: @@@@@ -#endif TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_proc_pcie_config exit" ); // end task, returning any errorlogs to IStepDisp - return l_errl; + return l_stepError.getErrorHandle(); } diff --git a/src/usr/hwpf/hwp/dram_initialization/makefile b/src/usr/hwpf/hwp/dram_initialization/makefile index 3f0918a74..38a9cd1b5 100644 --- a/src/usr/hwpf/hwp/dram_initialization/makefile +++ b/src/usr/hwpf/hwp/dram_initialization/makefile @@ -45,6 +45,7 @@ EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/proc_exit_cache_ EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/mss_memdiag +EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config ## NOTE: add new object files when you add a new HWP @@ -54,7 +55,8 @@ OBJS = dram_initialization.o \ mss_setup_bars.o \ proc_fab_smp.o \ proc_setup_bars.o \ - mss_maint_cmds.o + mss_maint_cmds.o \ + proc_pcie_config.o ## NOTE: add a new directory onto the vpaths when you add a new HWP @@ -64,6 +66,7 @@ VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/proc_exit_cache_contai VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/mss_memdiag +VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config include ${ROOTPATH}/config.mk diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.C b/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.C new file mode 100644 index 000000000..be10fc7f1 --- /dev/null +++ b/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.C @@ -0,0 +1,197 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: proc_pcie_config.C,v 1.1 2012/11/05 21:52:34 jmcgill Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_pcie_config.C,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2012 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! TITLE : proc_pcie_config.C +// *! DESCRIPTION : Perform PCIe PBCQ/AIB Inits (Phase 2, Steps 9-22) (FAPI) +// *! +// *! OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com +// *! +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapiHwpExecInitFile.H> +#include "proc_pcie_config.H" + +extern "C" { + +//------------------------------------------------------------------------------ +// Function definitions +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// function: apply PBCQ/AIB customization via SCOM initfile +// parameters: i_target => processor chip target +// returns: FAPI_RC_SUCCESS if initfile evaluation is successful, +// else error +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_pcie_config_pbcq( + const fapi::Target & i_target) +{ + fapi::ReturnCode rc; + std::vector<fapi::Target> targets; + + // mark function entry + FAPI_INF("proc_pcie_config_pbcq: Start"); + + do + { + // execute Phase2 SCOM initfile + targets.push_back(i_target); + FAPI_INF("proc_pcie_config_pbcq: Executing %s on %s", + PROC_PCIE_CONFIG_PHASE2_IF, i_target.toEcmdString()); + FAPI_EXEC_HWP( + rc, + fapiHwpExecInitFile, + targets, + PROC_PCIE_CONFIG_PHASE2_IF); + if (!rc.ok()) + { + FAPI_ERR("proc_pcie_config_pbcq: Error from fapiHwpExecInitfile executing %s on %s", + PROC_PCIE_CONFIG_PHASE2_IF, + i_target.toEcmdString()); + break; + } + } while(0); + + // mark function exit + FAPI_INF("proc_pcie_config_pbcq: End"); + return rc; +} + + +//------------------------------------------------------------------------------ +// function: initialize PBCQ FIRs +// clear FIR/WOF +// initialize FIR action settings +// reset FIR masks +// parameters: i_target => processor chip target +// returns: FAPI_RC_SUCCESS if all actions are successful, +// else error +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_pcie_config_pbcq_fir( + const fapi::Target & i_target) +{ + fapi::ReturnCode rc; + + ecmdDataBufferBase zero_data(64); + ecmdDataBufferBase ones_data(64); + + // mark function entry + FAPI_INF("proc_pcie_config_pbcq_fir: Start"); + + // loop over all PHBs + for (size_t i = 0; i < PROC_PCIE_CONFIG_NUM_PHB; i++) + { + // clear FIR + rc = fapiPutScom(i_target, + PROC_PCIE_CONFIG_PCIE_NEST_FIR[i], + zero_data); + if (!rc.ok()) + { + FAPI_ERR("proc_pcie_config_pbcq_fir: Error from fapiPutScom (PCIE%d_FIR_0x%08X)", + i, PROC_PCIE_CONFIG_PCIE_NEST_FIR[i]); + break; + } + + // clear FIR WOF + rc = fapiPutScom(i_target, + PROC_PCIE_CONFIG_PCIE_NEST_FIR_WOF[i], + zero_data); + if (!rc.ok()) + { + FAPI_ERR("proc_pcie_config_pbcq_fir: Error from fapiPutScom (PCIE%d_FIR_WOF_0x%08X)", + i, PROC_PCIE_CONFIG_PCIE_NEST_FIR_WOF[i]); + break; + } + + // clear FIR mask + rc = fapiPutScom(i_target, + PROC_PCIE_CONFIG_PCIE_NEST_FIR_MASK[i], + zero_data); + if (!rc.ok()) + { + FAPI_ERR("proc_pcie_config_pbcq_fir: Error from fapiPutScom (PCIE%d_FIR_MASK_0x%08X)", + i, PROC_PCIE_CONFIG_PCIE_NEST_FIR_MASK[i]); + break; + } + } + + // mark function exit + FAPI_INF("proc_pcie_config_pbcq_fir: End"); + return rc; +} + + +// HWP entry point, comments in header +fapi::ReturnCode proc_pcie_config( + const fapi::Target & i_target) +{ + fapi::ReturnCode rc; + + // mark HWP entry + FAPI_INF("proc_pcie_config: Start"); + + do + { + // check for supported target type + if (i_target.getType() != fapi::TARGET_TYPE_PROC_CHIP) + { + FAPI_ERR("proc_pcie_config: Unsupported target type"); + FAPI_SET_HWP_ERROR(rc, RC_PROC_PCIE_CONFIG_INVALID_TARGET); + break; + } + + // initialize PBCQ/AIB, configure PBCQ FIRs + rc = proc_pcie_config_pbcq(i_target); + if (!rc.ok()) + { + FAPI_ERR("proc_pcie_config: Error from proc_pcie_config_pbcq"); + break; + } + + rc = proc_pcie_config_pbcq_fir(i_target); + if (!rc.ok()) + { + FAPI_ERR("proc_pcie_config: Error from proc_pcie_config_pbcq_fir"); + break; + } + + } while(0); + + // mark HWP exit + FAPI_INF("proc_pcie_config: End"); + return rc; +} + + +} // extern "C" diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.H b/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.H new file mode 100644 index 000000000..c2920cb15 --- /dev/null +++ b/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.H @@ -0,0 +1,121 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: proc_pcie_config.H,v 1.1 2012/11/05 21:52:37 jmcgill Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_pcie_config.H,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2012 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! TITLE : proc_pcie_config.H +// *! DESCRIPTION : Perform PCIe PBCQ/AIB Inits (Phase 2, Steps 9-22) (FAPI) +// *! +// *! OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com +// *! +// *! ADDITIONAL COMMENTS : +// *! Configure PBCQ/AIB registers +// *! Clear PBCQ FIRs, setup for runtime +// *! +//------------------------------------------------------------------------------ + +#ifndef PROC_PCIE_CONFIG_H_ +#define PROC_PCIE_CONFIG_H_ + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi.H> +#include "p8_scom_addresses.H" + +//------------------------------------------------------------------------------ +// Constant definitions +//------------------------------------------------------------------------------ + +// SCOM initfile to execute +const char * const PROC_PCIE_CONFIG_PHASE2_IF = "p8.pe.phase2.scom.if"; + +// PCIe physical constants +const uint8_t PROC_PCIE_CONFIG_NUM_PHB = 3; + +const uint32_t PROC_PCIE_CONFIG_PCIE_NEST_FIR[PROC_PCIE_CONFIG_NUM_PHB] = +{ + PCIE0_FIR_0x02012000, + PCIE1_FIR_0x02012400, + PCIE2_FIR_0x02012800 +}; + +const uint32_t PROC_PCIE_CONFIG_PCIE_NEST_FIR_WOF[PROC_PCIE_CONFIG_NUM_PHB] = +{ + PCIE0_FIR_WOF_0x02012008, + PCIE1_FIR_WOF_0x02012408, + PCIE2_FIR_WOF_0x02012808 +}; + +const uint32_t PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION0[PROC_PCIE_CONFIG_NUM_PHB] = +{ + PCIE0_FIR_ACTION0_0x02012006, + PCIE1_FIR_ACTION0_0x02012406, + PCIE2_FIR_ACTION0_0x02012806 +}; + +const uint32_t PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION1[PROC_PCIE_CONFIG_NUM_PHB] = +{ + PCIE0_FIR_ACTION1_0x02012007, + PCIE1_FIR_ACTION1_0x02012407, + PCIE2_FIR_ACTION1_0x02012807 +}; + +const uint32_t PROC_PCIE_CONFIG_PCIE_NEST_FIR_MASK[PROC_PCIE_CONFIG_NUM_PHB] = +{ + PCIE0_FIR_MASK_0x02012003, + PCIE1_FIR_MASK_0x02012403, + PCIE2_FIR_MASK_0x02012803 +}; + +//------------------------------------------------------------------------------ +// Structure definitions +//------------------------------------------------------------------------------ + +// function pointer typedef definition for HWP call support +typedef fapi::ReturnCode +(*proc_pcie_config_FP_t)(const fapi::Target & i_target); + +extern "C" { + +//------------------------------------------------------------------------------ +// Function prototypes +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// function: perform PCIe PBCQ/AIB Inits (Phase 2, Steps 9-22) +// parameters: i_target => processor chip target +// returns: FAPI_RC_SUCCESS if all programming is successful, +// RC_PROC_PCIE_CONFIG_INVALID_TARGET if invalid target is supplied, +// else error +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_pcie_config(const fapi::Target & i_target); + + +} // extern "C" + +#endif // PROC_PCIE_CONFIG_H_ diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config_errors.xml b/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config_errors.xml new file mode 100644 index 000000000..53cb33dbc --- /dev/null +++ b/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config_errors.xml @@ -0,0 +1,30 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config_errors.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2012 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- Error definitions for proc_pcie_config --> +<hwpErrors> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_PCIE_CONFIG_INVALID_TARGET</rc> + <description>Invalid target type provided to HWP.</description> + </hwpError> +</hwpErrors> diff --git a/src/usr/hwpf/hwp/initfiles/p8.pe.phase2.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.pe.phase2.scom.initfile new file mode 100644 index 000000000..9fd4dcecb --- /dev/null +++ b/src/usr/hwpf/hwp/initfiles/p8.pe.phase2.scom.initfile @@ -0,0 +1,65 @@ +#-- $Id: p8.pe.phase2.scom.initfile,v 1.1 2012/11/05 21:39:35 jmcgill Exp $ +#------------------------------------------------------------------------------- +#-- +#-- (C) Copyright International Business Machines Corp. 2011 +#-- All Rights Reserved -- Property of IBM +#-- *** IBM Confidential *** +#-- +#-- TITLE : p8.pcie.phase2.scom.initfile +#-- DESCRIPTION : Perform PCIe PBCQ/AIB Inits (Phase 2, Steps 9-17) +#-- +#-- OWNER NAME : Joe McDonald Email: joemc@us.ibm.com +#-- OWNER NAME : Rick Mata Email: ricmata@us.ibm.com +#-- +#-------------------------------------------------------------------------------- + +SyntaxVersion = 1 + +#-------------------------------------------------------------------------------- +#-- Includes +#-------------------------------------------------------------------------------- + +#-------------------------------------------------------------------------------- +#-- Defines +#-------------------------------------------------------------------------------- + +define def_nest_freq_r0 = (SYS.ATTR_FREQ_PB >= 2200); +define def_nest_freq_r1 = ((SYS.ATTR_FREQ_PB <= 1700) && (SYS.ATTR_FREQ_PB < 2200)); +define def_nest_freq_r2 = (SYS.ATTR_FREQ_PB < 1700); + +#-------------------------------------------------------------------------------- +#-- SCOM initializations +#-------------------------------------------------------------------------------- + +#-- PBCQ Mode Control Register +scom 0x02012(0,4,8)0B { + bits, scom_data; + 26, 0b1; #-- enable enhanced IVE performance ordering +} + +#-- PCI Hardware Configuration 0 Register +scom 0x02012(0,4,8)18 { + bits, scom_data; + 17, 0b1; #-- disable out-of-order store behavior +} + +#-- PCI Nest Clock Trace Control Register +scom 0x02012(0,4,8)0D { + bits, scom_data; + 0:3, 0b1001; #-- enable trace, select inbound + address info +} + +#-- PB AIB Control/Status Register +scom 0x09012(0,4,8)0F { + bits, scom_data, expr; + 0:2, 0b011, (def_nest_freq_r0); #-- Maximum Ch0 command credit given to ETU + 0:2, 0b010, (def_nest_freq_r1); + 0:2, 0b001, (def_nest_freq_r2); + 3:5, 0b001, any; #-- Maximum Ch1 command credit given to ETU + 6:8, 0b011, (def_nest_freq_r0); #-- Maximum Ch2 command credit given to ETU + 6:8, 0b010, (def_nest_freq_r1 || def_nest_freq_r2); + 9:11, 0b000, any; #-- Maximum Ch3 command credit given to ETU + 12:13, 0b10, (def_nest_freq_r0 || def_nest_freq_r1); #-- Overcommit of inbound speed matching buffer + 12:13, 0b11, (def_nest_freq_r2); + 30:31, 0b11, any; #-- enable PCI clock tracing w/ ETU as default +}
\ No newline at end of file diff --git a/src/usr/hwpf/makefile b/src/usr/hwpf/makefile index 4a7f93da2..5d5311d8a 100644 --- a/src/usr/hwpf/makefile +++ b/src/usr/hwpf/makefile @@ -51,6 +51,7 @@ HWP_ERROR_XML_FILES = hwp/fapiHwpErrorInfo.xml \ hwp/thread_activate/proc_thread_control/proc_thread_control.xml \ hwp/erepair_errors.xml \ hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit_errors.xml \ + hwp/dram_initialization/proc_pcie_config/proc_pcie_config_errors.xml \ hwp/build_winkle_images/p8_set_pore_bar/p8_set_pore_bar_errors.xml \ hwp/build_winkle_images/p8_set_pore_bar/p8_pmc_deconfig_setup_errors.xml \ hwp/build_winkle_images/p8_set_pore_bar/p8_poreslw_errors.xml \ @@ -105,7 +106,8 @@ HWP_INITFILES = hwp/initfiles/sample.initfile \ hwp/initfiles/mba_def.initfile \ hwp/initfiles/cen_ddrphy.initfile \ hwp/initfiles/p8.fbc.scom.initfile \ - hwp/initfiles/p8.pe.phase1.scom.initfile + hwp/initfiles/p8.pe.phase1.scom.initfile \ + hwp/initfiles/p8.pe.phase2.scom.initfile HWP_IF_DEFINE_DIR = hwp/initfiles |
